HL = 0x2a ---------------- SET_REG2 HL = 0x002A jump(pop) ---------------- POP 0x07FE from mem[0x07FE] RET 0xAAAA [32mPASSED[0m life_universe_everything() (42 is correct) HL = 4 ---------------- SET_REG2 HL = 0x0004 HL = HL + SP {arg3} ---------------- REG 0x0004 = HL REG 0x07FA = SP ADD2 0x07FE = 0x0004 + 0x07FA SET_REG2 HL = 0x07FE IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FA = SP ADD2 0x07FC = 0x0002 + 0x07FA SET_REG2 IY = 0x07FC A = [IY {arg1}].b ---------------- REG 0x07FC = IY LOAD1 0x7 = mem[0x07FC] SET_REG1 A = 0x07 temp0.b = A ---------------- REG 0x0007 = A SET_REG1 temp0 = 0x07 temp1.b = [HL {arg3}].b ---------------- REG 0x07FE = HL LOAD1 0x4 = mem[0x07FE] SET_REG1 temp1 = 0x04 A = A + [HL {arg3}].b ---------------- REG 0x0007 = A REG 0x07FE = HL LOAD1 0x4 = mem[0x07FE] ADD1 0x0B = 0x07 + 0x04 SET_REG1 A = 0x0B flag:c = temp0.b u> 0xff - temp1.b ---------------- REG 0x0007 = temp0 REG 0x0004 = temp1 SUB1 0xFB = 0xFF - 0x04 CMP_UGT 0 = 0x0007 > 0x00FB SET_FLAG c = 0 C = A ---------------- REG 0x000B = A SET_REG1 C = 0x0B A = [IY + 1 {arg2}].b ---------------- REG 0x07FC = IY ADD2 0x07FD = 0x07FC + 0x0001 LOAD1 0x0 = mem[0x07FD] SET_REG1 A = 0x00 HL = HL + 1 {arg4} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = adc.b(A, [HL {arg4}].b, flag:c) ---------------- REG 0x0000 = A REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 L = C ---------------- REG 0x000B = C SET_REG1 L = 0x0B H = B ---------------- REG 0x0000 = B SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FA from mem[0x07FA] RET 0xAAAA [32mPASSED[0m add(4,7) (11 is correct) HL = 4 ---------------- SET_REG2 HL = 0x0004 HL = HL + SP {arg3} ---------------- REG 0x0004 = HL REG 0x07FA = SP ADD2 0x07FE = 0x0004 + 0x07FA SET_REG2 HL = 0x07FE IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FA = SP ADD2 0x07FC = 0x0002 + 0x07FA SET_REG2 IY = 0x07FC A = [IY {arg1}].b ---------------- REG 0x07FC = IY LOAD1 0x7 = mem[0x07FC] SET_REG1 A = 0x07 temp0.b = A ---------------- REG 0x0007 = A SET_REG1 temp0 = 0x07 temp1.b = [HL {arg3}].b ---------------- REG 0x07FE = HL LOAD1 0xFC = mem[0x07FE] SET_REG1 temp1 = 0xFC A = A + [HL {arg3}].b ---------------- REG 0x0007 = A REG 0x07FE = HL LOAD1 0xFC = mem[0x07FE] ADD1 0x03 = 0x07 + 0xFC SET_REG1 A = 0x03 flag:c = temp0.b u> 0xff - temp1.b ---------------- REG 0x0007 = temp0 REG 0x00FC = temp1 SUB1 0x03 = 0xFF - 0xFC CMP_UGT 1 = 0x0007 > 0x0003 SET_FLAG c = 1 C = A ---------------- REG 0x0003 = A SET_REG1 C = 0x03 A = [IY + 1 {arg2}].b ---------------- REG 0x07FC = IY ADD2 0x07FD = 0x07FC + 0x0001 LOAD1 0x0 = mem[0x07FD] SET_REG1 A = 0x00 HL = HL + 1 {arg4} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = adc.b(A, [HL {arg4}].b, flag:c) ---------------- REG 0x0000 = A REG 0x07FF = HL LOAD1 0xFF = mem[0x07FF] FLAG 1 = vm_flags[c] ADC 0x0100 = 0x0000 + 0x00FF + 1 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 L = C ---------------- REG 0x0003 = C SET_REG1 L = 0x03 H = B ---------------- REG 0x0000 = B SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FA from mem[0x07FA] RET 0xAAAA [32mPASSED[0m add(-4,7) (3 is correct) HL = 4 ---------------- SET_REG2 HL = 0x0004 HL = HL + SP {arg3} ---------------- REG 0x0004 = HL REG 0x07FA = SP ADD2 0x07FE = 0x0004 + 0x07FA SET_REG2 HL = 0x07FE IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FA = SP ADD2 0x07FC = 0x0002 + 0x07FA SET_REG2 IY = 0x07FC A = [IY {arg1}].b ---------------- REG 0x07FC = IY LOAD1 0xF9 = mem[0x07FC] SET_REG1 A = 0xF9 temp0.b = A ---------------- REG 0x00F9 = A SET_REG1 temp0 = 0xF9 temp1.b = [HL {arg3}].b ---------------- REG 0x07FE = HL LOAD1 0xFC = mem[0x07FE] SET_REG1 temp1 = 0xFC A = A + [HL {arg3}].b ---------------- REG 0x00F9 = A REG 0x07FE = HL LOAD1 0xFC = mem[0x07FE] ADD1 0xF5 = 0xF9 + 0xFC SET_REG1 A = 0xF5 flag:c = temp0.b u> 0xff - temp1.b ---------------- REG 0x00F9 = temp0 REG 0x00FC = temp1 SUB1 0x03 = 0xFF - 0xFC CMP_UGT 1 = 0x00F9 > 0x0003 SET_FLAG c = 1 C = A ---------------- REG 0x00F5 = A SET_REG1 C = 0xF5 A = [IY + 1 {arg2}].b ---------------- REG 0x07FC = IY ADD2 0x07FD = 0x07FC + 0x0001 LOAD1 0xFF = mem[0x07FD] SET_REG1 A = 0xFF HL = HL + 1 {arg4} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = adc.b(A, [HL {arg4}].b, flag:c) ---------------- REG 0x00FF = A REG 0x07FF = HL LOAD1 0xFF = mem[0x07FF] FLAG 1 = vm_flags[c] ADC 0x01FF = 0x00FF + 0x00FF + 1 SET_REG1 A = 0xFF B = A ---------------- REG 0x00FF = A SET_REG1 B = 0xFF L = C ---------------- REG 0x00F5 = C SET_REG1 L = 0xF5 H = B ---------------- REG 0x00FF = B SET_REG1 H = 0xFF jump(pop) ---------------- POP 0x07FA from mem[0x07FA] RET 0xAAAA [32mPASSED[0m add(-4,-7) (-11 is correct) HL = 4 ---------------- SET_REG2 HL = 0x0004 HL = HL + SP {arg3} ---------------- REG 0x0004 = HL REG 0x07FA = SP ADD2 0x07FE = 0x0004 + 0x07FA SET_REG2 HL = 0x07FE IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FA = SP ADD2 0x07FC = 0x0002 + 0x07FA SET_REG2 IY = 0x07FC A = [IY {arg1}].b ---------------- REG 0x07FC = IY LOAD1 0xC8 = mem[0x07FC] SET_REG1 A = 0xC8 temp0.b = A ---------------- REG 0x00C8 = A SET_REG1 temp0 = 0xC8 temp1.b = [HL {arg3}].b ---------------- REG 0x07FE = HL LOAD1 0x7B = mem[0x07FE] SET_REG1 temp1 = 0x7B A = A + [HL {arg3}].b ---------------- REG 0x00C8 = A REG 0x07FE = HL LOAD1 0x7B = mem[0x07FE] ADD1 0x43 = 0xC8 + 0x7B SET_REG1 A = 0x43 flag:c = temp0.b u> 0xff - temp1.b ---------------- REG 0x00C8 = temp0 REG 0x007B = temp1 SUB1 0x84 = 0xFF - 0x7B CMP_UGT 1 = 0x00C8 > 0x0084 SET_FLAG c = 1 C = A ---------------- REG 0x0043 = A SET_REG1 C = 0x43 A = [IY + 1 {arg2}].b ---------------- REG 0x07FC = IY ADD2 0x07FD = 0x07FC + 0x0001 LOAD1 0x1 = mem[0x07FD] SET_REG1 A = 0x01 HL = HL + 1 {arg4} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = adc.b(A, [HL {arg4}].b, flag:c) ---------------- REG 0x0001 = A REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] FLAG 1 = vm_flags[c] ADC 0x0002 = 0x0001 + 0x0000 + 1 SET_REG1 A = 0x02 B = A ---------------- REG 0x0002 = A SET_REG1 B = 0x02 L = C ---------------- REG 0x0043 = C SET_REG1 L = 0x43 H = B ---------------- REG 0x0002 = B SET_REG1 H = 0x02 jump(pop) ---------------- POP 0x07FA from mem[0x07FA] RET 0xAAAA [32mPASSED[0m add(123,456) (579 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A temp1.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x3 = mem[0x07FE] SET_REG1 temp1 = 0x03 A = A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x3 = mem[0x07FE] SUB1 0x07 = 0x0A - 0x03 SET_REG1 A = 0x07 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(temp1.b, 0x80)) | (test_bit(temp1.b, 0x80) & test_bit(temp0.b - temp1.b, 0x80))) | (test_bit(temp0.b - temp1.b, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = temp1 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = temp1 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = temp0 REG 0x0003 = temp1 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0003 = temp1 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 0 = vm_flags[c] RLC1 0x0 = 0x0 <<< 1 and carry = 0 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_unsigned_u8(3) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A temp1.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x7 = mem[0x07FE] SET_REG1 temp1 = 0x07 A = A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x7 = mem[0x07FE] SUB1 0x03 = 0x0A - 0x07 SET_REG1 A = 0x03 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(temp1.b, 0x80)) | (test_bit(temp1.b, 0x80) & test_bit(temp0.b - temp1.b, 0x80))) | (test_bit(temp0.b - temp1.b, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = temp1 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = temp1 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = temp0 REG 0x0007 = temp1 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0007 = temp1 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 0 = vm_flags[c] RLC1 0x0 = 0x0 <<< 1 and carry = 0 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_unsigned_u8(7) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A temp1.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xB = mem[0x07FE] SET_REG1 temp1 = 0x0B A = A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xB = mem[0x07FE] SUB1 0xFF = 0x0A - 0x0B SET_REG1 A = 0xFF flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(temp1.b, 0x80)) | (test_bit(temp1.b, 0x80) & test_bit(temp0.b - temp1.b, 0x80))) | (test_bit(temp0.b - temp1.b, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000B = temp1 TEST_BIT 0 = bool(0x000B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000B = temp1 TEST_BIT 0 = bool(0x000B & 0x0080) REG 0x000A = temp0 REG 0x000B = temp1 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x000B = temp1 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 1 = vm_flags[c] RLC1 0x1 = 0x0 <<< 1 and carry = 1 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_unsigned_u8(11) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A temp1.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xD = mem[0x07FE] SET_REG1 temp1 = 0x0D A = A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xD = mem[0x07FE] SUB1 0xFD = 0x0A - 0x0D SET_REG1 A = 0xFD flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(temp1.b, 0x80)) | (test_bit(temp1.b, 0x80) & test_bit(temp0.b - temp1.b, 0x80))) | (test_bit(temp0.b - temp1.b, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000D = temp1 TEST_BIT 0 = bool(0x000D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000D = temp1 TEST_BIT 0 = bool(0x000D & 0x0080) REG 0x000A = temp0 REG 0x000D = temp1 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x000D = temp1 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 1 = vm_flags[c] RLC1 0x1 = 0x0 <<< 1 and carry = 1 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_unsigned_u8(13) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A temp1.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x3 = mem[0x07FE] SET_REG1 temp1 = 0x03 A = A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x3 = mem[0x07FE] SUB1 0x07 = 0x0A - 0x03 SET_REG1 A = 0x07 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(temp1.b, 0x80)) | (test_bit(temp1.b, 0x80) & test_bit(temp0.b - temp1.b, 0x80))) | (test_bit(temp0.b - temp1.b, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = temp1 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = temp1 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = temp0 REG 0x0003 = temp1 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0003 = temp1 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 0 = vm_flags[c] RLC1 0x0 = 0x0 <<< 1 and carry = 0 SET_REG1 A = 0x00 A = 1 ^ A ---------------- REG 0x0000 = A XOR 0x0001 = 0x0001 ^ 0x0000 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m than_equal_10_unsigned_u8(3) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A temp1.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x7 = mem[0x07FE] SET_REG1 temp1 = 0x07 A = A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x7 = mem[0x07FE] SUB1 0x03 = 0x0A - 0x07 SET_REG1 A = 0x03 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(temp1.b, 0x80)) | (test_bit(temp1.b, 0x80) & test_bit(temp0.b - temp1.b, 0x80))) | (test_bit(temp0.b - temp1.b, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = temp1 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = temp1 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = temp0 REG 0x0007 = temp1 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0007 = temp1 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 0 = vm_flags[c] RLC1 0x0 = 0x0 <<< 1 and carry = 0 SET_REG1 A = 0x00 A = 1 ^ A ---------------- REG 0x0000 = A XOR 0x0001 = 0x0001 ^ 0x0000 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m than_equal_10_unsigned_u8(7) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A temp1.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xB = mem[0x07FE] SET_REG1 temp1 = 0x0B A = A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xB = mem[0x07FE] SUB1 0xFF = 0x0A - 0x0B SET_REG1 A = 0xFF flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(temp1.b, 0x80)) | (test_bit(temp1.b, 0x80) & test_bit(temp0.b - temp1.b, 0x80))) | (test_bit(temp0.b - temp1.b, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000B = temp1 TEST_BIT 0 = bool(0x000B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000B = temp1 TEST_BIT 0 = bool(0x000B & 0x0080) REG 0x000A = temp0 REG 0x000B = temp1 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x000B = temp1 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 1 = vm_flags[c] RLC1 0x1 = 0x0 <<< 1 and carry = 1 SET_REG1 A = 0x01 A = 1 ^ A ---------------- REG 0x0001 = A XOR 0x0000 = 0x0001 ^ 0x0001 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m than_equal_10_unsigned_u8(11) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A temp1.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xD = mem[0x07FE] SET_REG1 temp1 = 0x0D A = A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xD = mem[0x07FE] SUB1 0xFD = 0x0A - 0x0D SET_REG1 A = 0xFD flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(temp1.b, 0x80)) | (test_bit(temp1.b, 0x80) & test_bit(temp0.b - temp1.b, 0x80))) | (test_bit(temp0.b - temp1.b, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000D = temp1 TEST_BIT 0 = bool(0x000D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000D = temp1 TEST_BIT 0 = bool(0x000D & 0x0080) REG 0x000A = temp0 REG 0x000D = temp1 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x000D = temp1 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 1 = vm_flags[c] RLC1 0x1 = 0x0 <<< 1 and carry = 1 SET_REG1 A = 0x01 A = 1 ^ A ---------------- REG 0x0001 = A XOR 0x0000 = 0x0001 ^ 0x0001 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m than_equal_10_unsigned_u8(13) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 temp0.w = IY ---------------- REG 0x0002 = IY SET_REG2 temp0 = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE flag:pv = ((test_bit(temp0.w, 0x80) & test_bit(SP, 0x80)) | ((test_bit(temp0.w + SP, 0x80) ^ 0x1) & (test_bit(temp0.w, 0x80) ^ 0x1))) | ((test_bit(SP, 0x80) ^ 0x1) & test_bit(temp0.w + SP, 0x80)) ---------------- REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 A = A - [IY {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY LOAD1 0x3 = mem[0x07FE] SUB1 0x07 = 0x0A - 0x03 SET_REG1 A = 0x07 if (flag:pv ^ 0x1) then 7 @ 0x25c else 12 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x0007 = A ROL1(0x07, 1) returns 0x0E SET_REG1 A = 0x0E A = 1 & A ---------------- REG 0x000E = A AND 0x0000 = 0x0001 & 0x000E SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_signed_s8(3) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 temp0.w = IY ---------------- REG 0x0002 = IY SET_REG2 temp0 = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE flag:pv = ((test_bit(temp0.w, 0x80) & test_bit(SP, 0x80)) | ((test_bit(temp0.w + SP, 0x80) ^ 0x1) & (test_bit(temp0.w, 0x80) ^ 0x1))) | ((test_bit(SP, 0x80) ^ 0x1) & test_bit(temp0.w + SP, 0x80)) ---------------- REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 A = A - [IY {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY LOAD1 0x7 = mem[0x07FE] SUB1 0x03 = 0x0A - 0x07 SET_REG1 A = 0x03 if (flag:pv ^ 0x1) then 7 @ 0x25c else 12 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x0003 = A ROL1(0x03, 1) returns 0x06 SET_REG1 A = 0x06 A = 1 & A ---------------- REG 0x0006 = A AND 0x0000 = 0x0001 & 0x0006 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_signed_s8(7) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 temp0.w = IY ---------------- REG 0x0002 = IY SET_REG2 temp0 = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE flag:pv = ((test_bit(temp0.w, 0x80) & test_bit(SP, 0x80)) | ((test_bit(temp0.w + SP, 0x80) ^ 0x1) & (test_bit(temp0.w, 0x80) ^ 0x1))) | ((test_bit(SP, 0x80) ^ 0x1) & test_bit(temp0.w + SP, 0x80)) ---------------- REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 A = A - [IY {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY LOAD1 0xB = mem[0x07FE] SUB1 0xFF = 0x0A - 0x0B SET_REG1 A = 0xFF if (flag:pv ^ 0x1) then 7 @ 0x25c else 12 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x00FF = A ROL1(0xFF, 1) returns 0xFF SET_REG1 A = 0xFF A = 1 & A ---------------- REG 0x00FF = A AND 0x0001 = 0x0001 & 0x00FF SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_signed_s8(11) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 temp0.w = IY ---------------- REG 0x0002 = IY SET_REG2 temp0 = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE flag:pv = ((test_bit(temp0.w, 0x80) & test_bit(SP, 0x80)) | ((test_bit(temp0.w + SP, 0x80) ^ 0x1) & (test_bit(temp0.w, 0x80) ^ 0x1))) | ((test_bit(SP, 0x80) ^ 0x1) & test_bit(temp0.w + SP, 0x80)) ---------------- REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 A = A - [IY {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY LOAD1 0xD = mem[0x07FE] SUB1 0xFD = 0x0A - 0x0D SET_REG1 A = 0xFD if (flag:pv ^ 0x1) then 7 @ 0x25c else 12 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x00FD = A ROL1(0xFD, 1) returns 0xFB SET_REG1 A = 0xFB A = 1 & A ---------------- REG 0x00FB = A AND 0x0001 = 0x0001 & 0x00FB SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_signed_s8(13) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 temp0.w = IY ---------------- REG 0x0002 = IY SET_REG2 temp0 = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE flag:pv = ((test_bit(temp0.w, 0x80) & test_bit(SP, 0x80)) | ((test_bit(temp0.w + SP, 0x80) ^ 0x1) & (test_bit(temp0.w, 0x80) ^ 0x1))) | ((test_bit(SP, 0x80) ^ 0x1) & test_bit(temp0.w + SP, 0x80)) ---------------- REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 A = A - [IY {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY LOAD1 0x3 = mem[0x07FE] SUB1 0x07 = 0x0A - 0x03 SET_REG1 A = 0x07 if (flag:pv ^ 0x1) then 7 @ 0x273 else 13 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x0007 = A ROL1(0x07, 1) returns 0x0E SET_REG1 A = 0x0E A = 1 & A ---------------- REG 0x000E = A AND 0x0000 = 0x0001 & 0x000E SET_REG1 A = 0x00 A = 1 ^ A ---------------- REG 0x0000 = A XOR 0x0001 = 0x0001 ^ 0x0000 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_signed_s8(3) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 temp0.w = IY ---------------- REG 0x0002 = IY SET_REG2 temp0 = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE flag:pv = ((test_bit(temp0.w, 0x80) & test_bit(SP, 0x80)) | ((test_bit(temp0.w + SP, 0x80) ^ 0x1) & (test_bit(temp0.w, 0x80) ^ 0x1))) | ((test_bit(SP, 0x80) ^ 0x1) & test_bit(temp0.w + SP, 0x80)) ---------------- REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 A = A - [IY {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY LOAD1 0x7 = mem[0x07FE] SUB1 0x03 = 0x0A - 0x07 SET_REG1 A = 0x03 if (flag:pv ^ 0x1) then 7 @ 0x273 else 13 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x0003 = A ROL1(0x03, 1) returns 0x06 SET_REG1 A = 0x06 A = 1 & A ---------------- REG 0x0006 = A AND 0x0000 = 0x0001 & 0x0006 SET_REG1 A = 0x00 A = 1 ^ A ---------------- REG 0x0000 = A XOR 0x0001 = 0x0001 ^ 0x0000 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_signed_s8(7) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 temp0.w = IY ---------------- REG 0x0002 = IY SET_REG2 temp0 = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE flag:pv = ((test_bit(temp0.w, 0x80) & test_bit(SP, 0x80)) | ((test_bit(temp0.w + SP, 0x80) ^ 0x1) & (test_bit(temp0.w, 0x80) ^ 0x1))) | ((test_bit(SP, 0x80) ^ 0x1) & test_bit(temp0.w + SP, 0x80)) ---------------- REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 A = A - [IY {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY LOAD1 0xB = mem[0x07FE] SUB1 0xFF = 0x0A - 0x0B SET_REG1 A = 0xFF if (flag:pv ^ 0x1) then 7 @ 0x273 else 13 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x00FF = A ROL1(0xFF, 1) returns 0xFF SET_REG1 A = 0xFF A = 1 & A ---------------- REG 0x00FF = A AND 0x0001 = 0x0001 & 0x00FF SET_REG1 A = 0x01 A = 1 ^ A ---------------- REG 0x0001 = A XOR 0x0000 = 0x0001 ^ 0x0001 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_signed_s8(11) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 temp0.w = IY ---------------- REG 0x0002 = IY SET_REG2 temp0 = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE flag:pv = ((test_bit(temp0.w, 0x80) & test_bit(SP, 0x80)) | ((test_bit(temp0.w + SP, 0x80) ^ 0x1) & (test_bit(temp0.w, 0x80) ^ 0x1))) | ((test_bit(SP, 0x80) ^ 0x1) & test_bit(temp0.w + SP, 0x80)) ---------------- REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 TEST_BIT 0 = bool(0x0002 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x07FC = SP TEST_BIT 1 = bool(0x07FC & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 REG 0x0002 = temp0 REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC TEST_BIT 1 = bool(0x07FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 A = A - [IY {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY LOAD1 0xD = mem[0x07FE] SUB1 0xFD = 0x0A - 0x0D SET_REG1 A = 0xFD if (flag:pv ^ 0x1) then 7 @ 0x273 else 13 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x00FD = A ROL1(0xFD, 1) returns 0xFB SET_REG1 A = 0xFB A = 1 & A ---------------- REG 0x00FB = A AND 0x0001 = 0x0001 & 0x00FB SET_REG1 A = 0x01 A = 1 ^ A ---------------- REG 0x0001 = A XOR 0x0000 = 0x0001 ^ 0x0001 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_signed_s8(13) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x3 = mem[0x07FE] SET_REG1 temp0 = 0x03 A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x3 = mem[0x07FE] SUB1 0x07 = 0x0A - 0x03 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = temp0 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = temp0 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = A REG 0x0003 = temp0 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x0003 = temp0 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 cond:0 = flag:c ---------------- FLAG 0 = vm_flags[c] SET_FLAG cond:0 = 0 A = sbb.b(temp1.b, temp2.b, cond:0) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:c = (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) | (test_bit(temp2.b, 0x80) & test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80))) | (test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80) & (test_bit(temp1.b, 0x80) ^ 0x1)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 0 = vm_flags[c] RLC1 0x0 = 0x0 <<< 1 and carry = 0 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_unsigned(3) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x7 = mem[0x07FE] SET_REG1 temp0 = 0x07 A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x7 = mem[0x07FE] SUB1 0x03 = 0x0A - 0x07 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = A REG 0x0007 = temp0 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x0007 = temp0 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 cond:0 = flag:c ---------------- FLAG 0 = vm_flags[c] SET_FLAG cond:0 = 0 A = sbb.b(temp1.b, temp2.b, cond:0) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:c = (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) | (test_bit(temp2.b, 0x80) & test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80))) | (test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80) & (test_bit(temp1.b, 0x80) ^ 0x1)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 0 = vm_flags[c] RLC1 0x0 = 0x0 <<< 1 and carry = 0 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_unsigned(7) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xB = mem[0x07FE] SET_REG1 temp0 = 0x0B A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xB = mem[0x07FE] SUB1 0xFF = 0x0A - 0x0B flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000B = temp0 TEST_BIT 0 = bool(0x000B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000B = temp0 TEST_BIT 0 = bool(0x000B & 0x0080) REG 0x000A = A REG 0x000B = temp0 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x000B = temp0 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 cond:0 = flag:c ---------------- FLAG 1 = vm_flags[c] SET_FLAG cond:0 = 1 A = sbb.b(temp1.b, temp2.b, cond:0) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:c = (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) | (test_bit(temp2.b, 0x80) & test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80))) | (test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80) & (test_bit(temp1.b, 0x80) ^ 0x1)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 1 = vm_flags[c] RLC1 0x1 = 0x0 <<< 1 and carry = 1 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_unsigned(11) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xD = mem[0x07FE] SET_REG1 temp0 = 0x0D A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xD = mem[0x07FE] SUB1 0xFD = 0x0A - 0x0D flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000D = temp0 TEST_BIT 0 = bool(0x000D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000D = temp0 TEST_BIT 0 = bool(0x000D & 0x0080) REG 0x000A = A REG 0x000D = temp0 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x000D = temp0 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 cond:0 = flag:c ---------------- FLAG 1 = vm_flags[c] SET_FLAG cond:0 = 1 A = sbb.b(temp1.b, temp2.b, cond:0) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:c = (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) | (test_bit(temp2.b, 0x80) & test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80))) | (test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80) & (test_bit(temp1.b, 0x80) ^ 0x1)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 1 = vm_flags[c] RLC1 0x1 = 0x0 <<< 1 and carry = 1 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_unsigned(13) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x3 = mem[0x07FE] SET_REG1 temp0 = 0x03 A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x3 = mem[0x07FE] SUB1 0x07 = 0x0A - 0x03 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = temp0 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = temp0 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = A REG 0x0003 = temp0 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x0003 = temp0 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 cond:0 = flag:c ---------------- FLAG 0 = vm_flags[c] SET_FLAG cond:0 = 0 A = sbb.b(temp1.b, temp2.b, cond:0) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:c = (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) | (test_bit(temp2.b, 0x80) & test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80))) | (test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80) & (test_bit(temp1.b, 0x80) ^ 0x1)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 0 = vm_flags[c] RLC1 0x0 = 0x0 <<< 1 and carry = 0 SET_REG1 A = 0x00 A = 1 ^ A ---------------- REG 0x0000 = A XOR 0x0001 = 0x0001 ^ 0x0000 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_unsigned(3) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x7 = mem[0x07FE] SET_REG1 temp0 = 0x07 A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x7 = mem[0x07FE] SUB1 0x03 = 0x0A - 0x07 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = A REG 0x0007 = temp0 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x0007 = temp0 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 cond:0 = flag:c ---------------- FLAG 0 = vm_flags[c] SET_FLAG cond:0 = 0 A = sbb.b(temp1.b, temp2.b, cond:0) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:c = (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) | (test_bit(temp2.b, 0x80) & test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80))) | (test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80) & (test_bit(temp1.b, 0x80) ^ 0x1)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[cond:0] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 0 = vm_flags[c] RLC1 0x0 = 0x0 <<< 1 and carry = 0 SET_REG1 A = 0x00 A = 1 ^ A ---------------- REG 0x0000 = A XOR 0x0001 = 0x0001 ^ 0x0000 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_unsigned(7) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xB = mem[0x07FE] SET_REG1 temp0 = 0x0B A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xB = mem[0x07FE] SUB1 0xFF = 0x0A - 0x0B flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000B = temp0 TEST_BIT 0 = bool(0x000B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000B = temp0 TEST_BIT 0 = bool(0x000B & 0x0080) REG 0x000A = A REG 0x000B = temp0 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x000B = temp0 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 cond:0 = flag:c ---------------- FLAG 1 = vm_flags[c] SET_FLAG cond:0 = 1 A = sbb.b(temp1.b, temp2.b, cond:0) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:c = (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) | (test_bit(temp2.b, 0x80) & test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80))) | (test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80) & (test_bit(temp1.b, 0x80) ^ 0x1)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 1 = vm_flags[c] RLC1 0x1 = 0x0 <<< 1 and carry = 1 SET_REG1 A = 0x01 A = 1 ^ A ---------------- REG 0x0001 = A XOR 0x0000 = 0x0001 ^ 0x0001 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_unsigned(11) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xD = mem[0x07FE] SET_REG1 temp0 = 0x0D A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xD = mem[0x07FE] SUB1 0xFD = 0x0A - 0x0D flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000D = temp0 TEST_BIT 0 = bool(0x000D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000D = temp0 TEST_BIT 0 = bool(0x000D & 0x0080) REG 0x000A = A REG 0x000D = temp0 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x000D = temp0 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 cond:0 = flag:c ---------------- FLAG 1 = vm_flags[c] SET_FLAG cond:0 = 1 A = sbb.b(temp1.b, temp2.b, cond:0) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:c = (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) | (test_bit(temp2.b, 0x80) & test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80))) | (test_bit(sbb.b(temp1.b, temp2.b, cond:0), 0x80) & (test_bit(temp1.b, 0x80) ^ 0x1)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[cond:0] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 A = rlc.b(A, 1, flag:c) ---------------- REG 0x0000 = A FLAG 1 = vm_flags[c] RLC1 0x1 = 0x0 <<< 1 and carry = 1 SET_REG1 A = 0x01 A = 1 ^ A ---------------- REG 0x0001 = A XOR 0x0000 = 0x0001 ^ 0x0001 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_unsigned(13) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x3 = mem[0x07FE] SET_REG1 temp0 = 0x03 A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x3 = mem[0x07FE] SUB1 0x07 = 0x0A - 0x03 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = temp0 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = temp0 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = A REG 0x0003 = temp0 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x0003 = temp0 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 A = sbb.b(temp1.b, temp2.b, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(temp2.b, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) & test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 12 @ 0x2c1 else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x0000 = A ROL1(0x00, 1) returns 0x00 SET_REG1 A = 0x00 A = 1 & A ---------------- REG 0x0000 = A AND 0x0000 = 0x0001 & 0x0000 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_signed(3) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x7 = mem[0x07FE] SET_REG1 temp0 = 0x07 A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x7 = mem[0x07FE] SUB1 0x03 = 0x0A - 0x07 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = A REG 0x0007 = temp0 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x0007 = temp0 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 A = sbb.b(temp1.b, temp2.b, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(temp2.b, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) & test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 12 @ 0x2c1 else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x0000 = A ROL1(0x00, 1) returns 0x00 SET_REG1 A = 0x00 A = 1 & A ---------------- REG 0x0000 = A AND 0x0000 = 0x0001 & 0x0000 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_signed(7) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xB = mem[0x07FE] SET_REG1 temp0 = 0x0B A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xB = mem[0x07FE] SUB1 0xFF = 0x0A - 0x0B flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000B = temp0 TEST_BIT 0 = bool(0x000B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000B = temp0 TEST_BIT 0 = bool(0x000B & 0x0080) REG 0x000A = A REG 0x000B = temp0 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x000B = temp0 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 A = sbb.b(temp1.b, temp2.b, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(temp2.b, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) & test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 12 @ 0x2c1 else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x00FF = A ROL1(0xFF, 1) returns 0xFF SET_REG1 A = 0xFF A = 1 & A ---------------- REG 0x00FF = A AND 0x0001 = 0x0001 & 0x00FF SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_signed(11) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xD = mem[0x07FE] SET_REG1 temp0 = 0x0D A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xD = mem[0x07FE] SUB1 0xFD = 0x0A - 0x0D flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000D = temp0 TEST_BIT 0 = bool(0x000D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000D = temp0 TEST_BIT 0 = bool(0x000D & 0x0080) REG 0x000A = A REG 0x000D = temp0 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x000D = temp0 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 A = sbb.b(temp1.b, temp2.b, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(temp2.b, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) & test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 12 @ 0x2c1 else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x00FF = A ROL1(0xFF, 1) returns 0xFF SET_REG1 A = 0xFF A = 1 & A ---------------- REG 0x00FF = A AND 0x0001 = 0x0001 & 0x00FF SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_greater_10_signed(13) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x3 = mem[0x07FE] SET_REG1 temp0 = 0x03 A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x3 = mem[0x07FE] SUB1 0x07 = 0x0A - 0x03 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = temp0 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = temp0 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = A REG 0x0003 = temp0 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x0003 = temp0 SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 A = sbb.b(temp1.b, temp2.b, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(temp2.b, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) & test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 12 @ 0x2dd else 18 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x0000 = A ROL1(0x00, 1) returns 0x00 SET_REG1 A = 0x00 A = 1 & A ---------------- REG 0x0000 = A AND 0x0000 = 0x0001 & 0x0000 SET_REG1 A = 0x00 A = 1 ^ A ---------------- REG 0x0000 = A XOR 0x0001 = 0x0001 ^ 0x0000 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_signed(3) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0x7 = mem[0x07FE] SET_REG1 temp0 = 0x07 A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0x7 = mem[0x07FE] SUB1 0x03 = 0x0A - 0x07 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = A REG 0x0007 = temp0 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x0007 = temp0 SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 A = sbb.b(temp1.b, temp2.b, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(temp2.b, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) & test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 12 @ 0x2dd else 18 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x0000 = A ROL1(0x00, 1) returns 0x00 SET_REG1 A = 0x00 A = 1 & A ---------------- REG 0x0000 = A AND 0x0000 = 0x0001 & 0x0000 SET_REG1 A = 0x00 A = 1 ^ A ---------------- REG 0x0000 = A XOR 0x0001 = 0x0001 ^ 0x0000 SET_REG1 A = 0x01 L = A ---------------- REG 0x0001 = A SET_REG1 L = 0x01 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_signed(7) (1 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xB = mem[0x07FE] SET_REG1 temp0 = 0x0B A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xB = mem[0x07FE] SUB1 0xFF = 0x0A - 0x0B flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000B = temp0 TEST_BIT 0 = bool(0x000B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000B = temp0 TEST_BIT 0 = bool(0x000B & 0x0080) REG 0x000A = A REG 0x000B = temp0 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x000B = temp0 SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 A = sbb.b(temp1.b, temp2.b, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(temp2.b, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) & test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 12 @ 0x2dd else 18 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x00FF = A ROL1(0xFF, 1) returns 0xFF SET_REG1 A = 0xFF A = 1 & A ---------------- REG 0x00FF = A AND 0x0001 = 0x0001 & 0x00FF SET_REG1 A = 0x01 A = 1 ^ A ---------------- REG 0x0001 = A XOR 0x0000 = 0x0001 ^ 0x0001 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_signed(11) (0 is correct) A = 0xa ---------------- SET_REG1 A = 0x0A IY = 2 ---------------- SET_REG2 IY = 0x0002 IY = IY + SP {arg1} ---------------- REG 0x0002 = IY REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 IY = 0x07FE temp0.b = [IY {arg1}].b ---------------- REG 0x07FE = IY LOAD1 0xD = mem[0x07FE] SET_REG1 temp0 = 0x0D A - [IY + 0 {arg1}].b ---------------- REG 0x000A = A REG 0x07FE = IY ADD2 0x07FE = 0x07FE + 0x0000 LOAD1 0xD = mem[0x07FE] SUB1 0xFD = 0x0A - 0x0D flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(temp0.b, 0x80)) | (test_bit(temp0.b, 0x80) & test_bit(A - temp0.b, 0x80))) | (test_bit(A - temp0.b, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000D = temp0 TEST_BIT 0 = bool(0x000D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000D = temp0 TEST_BIT 0 = bool(0x000D & 0x0080) REG 0x000A = A REG 0x000D = temp0 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = A REG 0x000D = temp0 SUB1 0xFD = 0x0A - 0x0D TEST_BIT 1 = bool(0x00FD & 0x0080) REG 0x000A = A TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 A = 0 ---------------- SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 temp2.b = [IY + 1 {arg2}].b ---------------- REG 0x07FE = IY ADD2 0x07FF = 0x07FE + 0x0001 LOAD1 0x0 = mem[0x07FF] SET_REG1 temp2 = 0x00 A = sbb.b(temp1.b, temp2.b, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(temp2.b, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(temp2.b, 0x80)) & test_bit(sbb.b(temp1.b, temp2.b, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = temp2 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = temp2 FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 12 @ 0x2dd else 18 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 A = rol.b(A, 1) ---------------- REG 0x00FF = A ROL1(0xFF, 1) returns 0xFF SET_REG1 A = 0xFF A = 1 & A ---------------- REG 0x00FF = A AND 0x0001 = 0x0001 & 0x00FF SET_REG1 A = 0x01 A = 1 ^ A ---------------- REG 0x0001 = A XOR 0x0000 = 0x0001 ^ 0x0001 SET_REG1 A = 0x00 L = A ---------------- REG 0x0000 = A SET_REG1 L = 0x00 H = 0 ---------------- SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m is_less_than_equal_10_signed(13) (0 is correct) BC = 0 ---------------- SET_REG2 BC = 0x0000 DE = 1 ---------------- SET_REG2 DE = 0x0001 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x4 = mem[0x07FE] SET_REG1 A = 0x04 temp0.b = A ---------------- REG 0x0004 = A SET_REG1 temp0 = 0x04 A = A - E ---------------- REG 0x0004 = A REG 0x0001 = E SUB1 0x03 = 0x04 - 0x01 SET_REG1 A = 0x03 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0004 = temp0 TEST_BIT 0 = bool(0x0004 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x0004 = temp0 REG 0x0001 = E SUB1 0x03 = 0x04 - 0x01 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0004 = temp0 REG 0x0001 = E SUB1 0x03 = 0x04 - 0x01 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x0004 = temp0 TEST_BIT 0 = bool(0x0004 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0000 = C SET_REG1 A = 0x00 temp2.b = A ---------------- REG 0x0000 = A SET_REG1 temp2 = 0x00 A = A + E ---------------- REG 0x0000 = A REG 0x0001 = E ADD1 0x01 = 0x00 + 0x01 SET_REG1 A = 0x01 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0000 = temp2 REG 0x0001 = E SUB1 0xFE = 0xFF - 0x01 CMP_UGT 0 = 0x0000 > 0x00FE SET_FLAG c = 0 C = A ---------------- REG 0x0001 = A SET_REG1 C = 0x01 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0001 = DE ADD2 0x0002 = 0x0001 + 0x0001 SET_REG2 DE = 0x0002 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x4 = mem[0x07FE] SET_REG1 A = 0x04 temp0.b = A ---------------- REG 0x0004 = A SET_REG1 temp0 = 0x04 A = A - E ---------------- REG 0x0004 = A REG 0x0002 = E SUB1 0x02 = 0x04 - 0x02 SET_REG1 A = 0x02 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0004 = temp0 TEST_BIT 0 = bool(0x0004 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x0004 = temp0 REG 0x0002 = E SUB1 0x02 = 0x04 - 0x02 TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0004 = temp0 REG 0x0002 = E SUB1 0x02 = 0x04 - 0x02 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x0004 = temp0 TEST_BIT 0 = bool(0x0004 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0001 = C SET_REG1 A = 0x01 temp2.b = A ---------------- REG 0x0001 = A SET_REG1 temp2 = 0x01 A = A + E ---------------- REG 0x0001 = A REG 0x0002 = E ADD1 0x03 = 0x01 + 0x02 SET_REG1 A = 0x03 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0001 = temp2 REG 0x0002 = E SUB1 0xFD = 0xFF - 0x02 CMP_UGT 0 = 0x0001 > 0x00FD SET_FLAG c = 0 C = A ---------------- REG 0x0003 = A SET_REG1 C = 0x03 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0002 = DE ADD2 0x0003 = 0x0002 + 0x0001 SET_REG2 DE = 0x0003 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x4 = mem[0x07FE] SET_REG1 A = 0x04 temp0.b = A ---------------- REG 0x0004 = A SET_REG1 temp0 = 0x04 A = A - E ---------------- REG 0x0004 = A REG 0x0003 = E SUB1 0x01 = 0x04 - 0x03 SET_REG1 A = 0x01 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0004 = temp0 TEST_BIT 0 = bool(0x0004 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x0004 = temp0 REG 0x0003 = E SUB1 0x01 = 0x04 - 0x03 TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0004 = temp0 REG 0x0003 = E SUB1 0x01 = 0x04 - 0x03 TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x0004 = temp0 TEST_BIT 0 = bool(0x0004 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0003 = C SET_REG1 A = 0x03 temp2.b = A ---------------- REG 0x0003 = A SET_REG1 temp2 = 0x03 A = A + E ---------------- REG 0x0003 = A REG 0x0003 = E ADD1 0x06 = 0x03 + 0x03 SET_REG1 A = 0x06 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0003 = temp2 REG 0x0003 = E SUB1 0xFC = 0xFF - 0x03 CMP_UGT 0 = 0x0003 > 0x00FC SET_FLAG c = 0 C = A ---------------- REG 0x0006 = A SET_REG1 C = 0x06 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0003 = DE ADD2 0x0004 = 0x0003 + 0x0001 SET_REG2 DE = 0x0004 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x4 = mem[0x07FE] SET_REG1 A = 0x04 temp0.b = A ---------------- REG 0x0004 = A SET_REG1 temp0 = 0x04 A = A - E ---------------- REG 0x0004 = A REG 0x0004 = E SUB1 0x00 = 0x04 - 0x04 SET_REG1 A = 0x00 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0004 = temp0 TEST_BIT 0 = bool(0x0004 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x0004 = temp0 REG 0x0004 = E SUB1 0x00 = 0x04 - 0x04 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0004 = temp0 REG 0x0004 = E SUB1 0x00 = 0x04 - 0x04 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0004 = temp0 TEST_BIT 0 = bool(0x0004 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0006 = C SET_REG1 A = 0x06 temp2.b = A ---------------- REG 0x0006 = A SET_REG1 temp2 = 0x06 A = A + E ---------------- REG 0x0006 = A REG 0x0004 = E ADD1 0x0A = 0x06 + 0x04 SET_REG1 A = 0x0A flag:c = temp2.b u> 0xff - E ---------------- REG 0x0006 = temp2 REG 0x0004 = E SUB1 0xFB = 0xFF - 0x04 CMP_UGT 0 = 0x0006 > 0x00FB SET_FLAG c = 0 C = A ---------------- REG 0x000A = A SET_REG1 C = 0x0A A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0004 = DE ADD2 0x0005 = 0x0004 + 0x0001 SET_REG2 DE = 0x0005 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x4 = mem[0x07FE] SET_REG1 A = 0x04 temp0.b = A ---------------- REG 0x0004 = A SET_REG1 temp0 = 0x04 A = A - E ---------------- REG 0x0004 = A REG 0x0005 = E SUB1 0xFF = 0x04 - 0x05 SET_REG1 A = 0xFF flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0004 = temp0 TEST_BIT 0 = bool(0x0004 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) REG 0x0004 = temp0 REG 0x0005 = E SUB1 0xFF = 0x04 - 0x05 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0004 = temp0 REG 0x0005 = E SUB1 0xFF = 0x04 - 0x05 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0004 = temp0 TEST_BIT 0 = bool(0x0004 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 1 = vm_flags[s] L = C ---------------- REG 0x000A = C SET_REG1 L = 0x0A H = B ---------------- REG 0x0000 = B SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m triangle_up(4) (10 is correct) BC = 0 ---------------- SET_REG2 BC = 0x0000 DE = 1 ---------------- SET_REG2 DE = 0x0001 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x7 = mem[0x07FE] SET_REG1 A = 0x07 temp0.b = A ---------------- REG 0x0007 = A SET_REG1 temp0 = 0x07 A = A - E ---------------- REG 0x0007 = A REG 0x0001 = E SUB1 0x06 = 0x07 - 0x01 SET_REG1 A = 0x06 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x0007 = temp0 REG 0x0001 = E SUB1 0x06 = 0x07 - 0x01 TEST_BIT 0 = bool(0x0006 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0007 = temp0 REG 0x0001 = E SUB1 0x06 = 0x07 - 0x01 TEST_BIT 0 = bool(0x0006 & 0x0080) REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0000 = C SET_REG1 A = 0x00 temp2.b = A ---------------- REG 0x0000 = A SET_REG1 temp2 = 0x00 A = A + E ---------------- REG 0x0000 = A REG 0x0001 = E ADD1 0x01 = 0x00 + 0x01 SET_REG1 A = 0x01 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0000 = temp2 REG 0x0001 = E SUB1 0xFE = 0xFF - 0x01 CMP_UGT 0 = 0x0000 > 0x00FE SET_FLAG c = 0 C = A ---------------- REG 0x0001 = A SET_REG1 C = 0x01 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0001 = DE ADD2 0x0002 = 0x0001 + 0x0001 SET_REG2 DE = 0x0002 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x7 = mem[0x07FE] SET_REG1 A = 0x07 temp0.b = A ---------------- REG 0x0007 = A SET_REG1 temp0 = 0x07 A = A - E ---------------- REG 0x0007 = A REG 0x0002 = E SUB1 0x05 = 0x07 - 0x02 SET_REG1 A = 0x05 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x0007 = temp0 REG 0x0002 = E SUB1 0x05 = 0x07 - 0x02 TEST_BIT 0 = bool(0x0005 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0007 = temp0 REG 0x0002 = E SUB1 0x05 = 0x07 - 0x02 TEST_BIT 0 = bool(0x0005 & 0x0080) REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0001 = C SET_REG1 A = 0x01 temp2.b = A ---------------- REG 0x0001 = A SET_REG1 temp2 = 0x01 A = A + E ---------------- REG 0x0001 = A REG 0x0002 = E ADD1 0x03 = 0x01 + 0x02 SET_REG1 A = 0x03 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0001 = temp2 REG 0x0002 = E SUB1 0xFD = 0xFF - 0x02 CMP_UGT 0 = 0x0001 > 0x00FD SET_FLAG c = 0 C = A ---------------- REG 0x0003 = A SET_REG1 C = 0x03 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0002 = DE ADD2 0x0003 = 0x0002 + 0x0001 SET_REG2 DE = 0x0003 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x7 = mem[0x07FE] SET_REG1 A = 0x07 temp0.b = A ---------------- REG 0x0007 = A SET_REG1 temp0 = 0x07 A = A - E ---------------- REG 0x0007 = A REG 0x0003 = E SUB1 0x04 = 0x07 - 0x03 SET_REG1 A = 0x04 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x0007 = temp0 REG 0x0003 = E SUB1 0x04 = 0x07 - 0x03 TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0007 = temp0 REG 0x0003 = E SUB1 0x04 = 0x07 - 0x03 TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0003 = C SET_REG1 A = 0x03 temp2.b = A ---------------- REG 0x0003 = A SET_REG1 temp2 = 0x03 A = A + E ---------------- REG 0x0003 = A REG 0x0003 = E ADD1 0x06 = 0x03 + 0x03 SET_REG1 A = 0x06 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0003 = temp2 REG 0x0003 = E SUB1 0xFC = 0xFF - 0x03 CMP_UGT 0 = 0x0003 > 0x00FC SET_FLAG c = 0 C = A ---------------- REG 0x0006 = A SET_REG1 C = 0x06 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0003 = DE ADD2 0x0004 = 0x0003 + 0x0001 SET_REG2 DE = 0x0004 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x7 = mem[0x07FE] SET_REG1 A = 0x07 temp0.b = A ---------------- REG 0x0007 = A SET_REG1 temp0 = 0x07 A = A - E ---------------- REG 0x0007 = A REG 0x0004 = E SUB1 0x03 = 0x07 - 0x04 SET_REG1 A = 0x03 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x0007 = temp0 REG 0x0004 = E SUB1 0x03 = 0x07 - 0x04 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0007 = temp0 REG 0x0004 = E SUB1 0x03 = 0x07 - 0x04 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0006 = C SET_REG1 A = 0x06 temp2.b = A ---------------- REG 0x0006 = A SET_REG1 temp2 = 0x06 A = A + E ---------------- REG 0x0006 = A REG 0x0004 = E ADD1 0x0A = 0x06 + 0x04 SET_REG1 A = 0x0A flag:c = temp2.b u> 0xff - E ---------------- REG 0x0006 = temp2 REG 0x0004 = E SUB1 0xFB = 0xFF - 0x04 CMP_UGT 0 = 0x0006 > 0x00FB SET_FLAG c = 0 C = A ---------------- REG 0x000A = A SET_REG1 C = 0x0A A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0004 = DE ADD2 0x0005 = 0x0004 + 0x0001 SET_REG2 DE = 0x0005 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x7 = mem[0x07FE] SET_REG1 A = 0x07 temp0.b = A ---------------- REG 0x0007 = A SET_REG1 temp0 = 0x07 A = A - E ---------------- REG 0x0007 = A REG 0x0005 = E SUB1 0x02 = 0x07 - 0x05 SET_REG1 A = 0x02 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) REG 0x0007 = temp0 REG 0x0005 = E SUB1 0x02 = 0x07 - 0x05 TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0007 = temp0 REG 0x0005 = E SUB1 0x02 = 0x07 - 0x05 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x000A = C SET_REG1 A = 0x0A temp2.b = A ---------------- REG 0x000A = A SET_REG1 temp2 = 0x0A A = A + E ---------------- REG 0x000A = A REG 0x0005 = E ADD1 0x0F = 0x0A + 0x05 SET_REG1 A = 0x0F flag:c = temp2.b u> 0xff - E ---------------- REG 0x000A = temp2 REG 0x0005 = E SUB1 0xFA = 0xFF - 0x05 CMP_UGT 0 = 0x000A > 0x00FA SET_FLAG c = 0 C = A ---------------- REG 0x000F = A SET_REG1 C = 0x0F A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0005 = DE ADD2 0x0006 = 0x0005 + 0x0001 SET_REG2 DE = 0x0006 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x7 = mem[0x07FE] SET_REG1 A = 0x07 temp0.b = A ---------------- REG 0x0007 = A SET_REG1 temp0 = 0x07 A = A - E ---------------- REG 0x0007 = A REG 0x0006 = E SUB1 0x01 = 0x07 - 0x06 SET_REG1 A = 0x01 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) REG 0x0007 = temp0 REG 0x0006 = E SUB1 0x01 = 0x07 - 0x06 TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0007 = temp0 REG 0x0006 = E SUB1 0x01 = 0x07 - 0x06 TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x000F = C SET_REG1 A = 0x0F temp2.b = A ---------------- REG 0x000F = A SET_REG1 temp2 = 0x0F A = A + E ---------------- REG 0x000F = A REG 0x0006 = E ADD1 0x15 = 0x0F + 0x06 SET_REG1 A = 0x15 flag:c = temp2.b u> 0xff - E ---------------- REG 0x000F = temp2 REG 0x0006 = E SUB1 0xF9 = 0xFF - 0x06 CMP_UGT 0 = 0x000F > 0x00F9 SET_FLAG c = 0 C = A ---------------- REG 0x0015 = A SET_REG1 C = 0x15 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0006 = DE ADD2 0x0007 = 0x0006 + 0x0001 SET_REG2 DE = 0x0007 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x7 = mem[0x07FE] SET_REG1 A = 0x07 temp0.b = A ---------------- REG 0x0007 = A SET_REG1 temp0 = 0x07 A = A - E ---------------- REG 0x0007 = A REG 0x0007 = E SUB1 0x00 = 0x07 - 0x07 SET_REG1 A = 0x00 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x0007 = temp0 REG 0x0007 = E SUB1 0x00 = 0x07 - 0x07 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0007 = temp0 REG 0x0007 = E SUB1 0x00 = 0x07 - 0x07 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0015 = C SET_REG1 A = 0x15 temp2.b = A ---------------- REG 0x0015 = A SET_REG1 temp2 = 0x15 A = A + E ---------------- REG 0x0015 = A REG 0x0007 = E ADD1 0x1C = 0x15 + 0x07 SET_REG1 A = 0x1C flag:c = temp2.b u> 0xff - E ---------------- REG 0x0015 = temp2 REG 0x0007 = E SUB1 0xF8 = 0xFF - 0x07 CMP_UGT 0 = 0x0015 > 0x00F8 SET_FLAG c = 0 C = A ---------------- REG 0x001C = A SET_REG1 C = 0x1C A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0007 = DE ADD2 0x0008 = 0x0007 + 0x0001 SET_REG2 DE = 0x0008 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x7 = mem[0x07FE] SET_REG1 A = 0x07 temp0.b = A ---------------- REG 0x0007 = A SET_REG1 temp0 = 0x07 A = A - E ---------------- REG 0x0007 = A REG 0x0008 = E SUB1 0xFF = 0x07 - 0x08 SET_REG1 A = 0xFF flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0008 = E TEST_BIT 0 = bool(0x0008 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0008 = E TEST_BIT 0 = bool(0x0008 & 0x0080) REG 0x0007 = temp0 REG 0x0008 = E SUB1 0xFF = 0x07 - 0x08 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0007 = temp0 REG 0x0008 = E SUB1 0xFF = 0x07 - 0x08 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0007 = temp0 TEST_BIT 0 = bool(0x0007 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 1 = vm_flags[s] L = C ---------------- REG 0x001C = C SET_REG1 L = 0x1C H = B ---------------- REG 0x0000 = B SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m triangle_up(7) (28 is correct) BC = 0 ---------------- SET_REG2 BC = 0x0000 DE = 1 ---------------- SET_REG2 DE = 0x0001 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x0001 = E SUB1 0x09 = 0x0A - 0x01 SET_REG1 A = 0x09 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x000A = temp0 REG 0x0001 = E SUB1 0x09 = 0x0A - 0x01 TEST_BIT 0 = bool(0x0009 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0001 = E SUB1 0x09 = 0x0A - 0x01 TEST_BIT 0 = bool(0x0009 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0000 = C SET_REG1 A = 0x00 temp2.b = A ---------------- REG 0x0000 = A SET_REG1 temp2 = 0x00 A = A + E ---------------- REG 0x0000 = A REG 0x0001 = E ADD1 0x01 = 0x00 + 0x01 SET_REG1 A = 0x01 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0000 = temp2 REG 0x0001 = E SUB1 0xFE = 0xFF - 0x01 CMP_UGT 0 = 0x0000 > 0x00FE SET_FLAG c = 0 C = A ---------------- REG 0x0001 = A SET_REG1 C = 0x01 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0001 = DE ADD2 0x0002 = 0x0001 + 0x0001 SET_REG2 DE = 0x0002 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x0002 = E SUB1 0x08 = 0x0A - 0x02 SET_REG1 A = 0x08 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x000A = temp0 REG 0x0002 = E SUB1 0x08 = 0x0A - 0x02 TEST_BIT 0 = bool(0x0008 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0002 = E SUB1 0x08 = 0x0A - 0x02 TEST_BIT 0 = bool(0x0008 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0001 = C SET_REG1 A = 0x01 temp2.b = A ---------------- REG 0x0001 = A SET_REG1 temp2 = 0x01 A = A + E ---------------- REG 0x0001 = A REG 0x0002 = E ADD1 0x03 = 0x01 + 0x02 SET_REG1 A = 0x03 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0001 = temp2 REG 0x0002 = E SUB1 0xFD = 0xFF - 0x02 CMP_UGT 0 = 0x0001 > 0x00FD SET_FLAG c = 0 C = A ---------------- REG 0x0003 = A SET_REG1 C = 0x03 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0002 = DE ADD2 0x0003 = 0x0002 + 0x0001 SET_REG2 DE = 0x0003 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x0003 = E SUB1 0x07 = 0x0A - 0x03 SET_REG1 A = 0x07 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = temp0 REG 0x0003 = E SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0003 = E SUB1 0x07 = 0x0A - 0x03 TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0003 = C SET_REG1 A = 0x03 temp2.b = A ---------------- REG 0x0003 = A SET_REG1 temp2 = 0x03 A = A + E ---------------- REG 0x0003 = A REG 0x0003 = E ADD1 0x06 = 0x03 + 0x03 SET_REG1 A = 0x06 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0003 = temp2 REG 0x0003 = E SUB1 0xFC = 0xFF - 0x03 CMP_UGT 0 = 0x0003 > 0x00FC SET_FLAG c = 0 C = A ---------------- REG 0x0006 = A SET_REG1 C = 0x06 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0003 = DE ADD2 0x0004 = 0x0003 + 0x0001 SET_REG2 DE = 0x0004 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x0004 = E SUB1 0x06 = 0x0A - 0x04 SET_REG1 A = 0x06 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x000A = temp0 REG 0x0004 = E SUB1 0x06 = 0x0A - 0x04 TEST_BIT 0 = bool(0x0006 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0004 = E SUB1 0x06 = 0x0A - 0x04 TEST_BIT 0 = bool(0x0006 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0006 = C SET_REG1 A = 0x06 temp2.b = A ---------------- REG 0x0006 = A SET_REG1 temp2 = 0x06 A = A + E ---------------- REG 0x0006 = A REG 0x0004 = E ADD1 0x0A = 0x06 + 0x04 SET_REG1 A = 0x0A flag:c = temp2.b u> 0xff - E ---------------- REG 0x0006 = temp2 REG 0x0004 = E SUB1 0xFB = 0xFF - 0x04 CMP_UGT 0 = 0x0006 > 0x00FB SET_FLAG c = 0 C = A ---------------- REG 0x000A = A SET_REG1 C = 0x0A A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0004 = DE ADD2 0x0005 = 0x0004 + 0x0001 SET_REG2 DE = 0x0005 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x0005 = E SUB1 0x05 = 0x0A - 0x05 SET_REG1 A = 0x05 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) REG 0x000A = temp0 REG 0x0005 = E SUB1 0x05 = 0x0A - 0x05 TEST_BIT 0 = bool(0x0005 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0005 = E SUB1 0x05 = 0x0A - 0x05 TEST_BIT 0 = bool(0x0005 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x000A = C SET_REG1 A = 0x0A temp2.b = A ---------------- REG 0x000A = A SET_REG1 temp2 = 0x0A A = A + E ---------------- REG 0x000A = A REG 0x0005 = E ADD1 0x0F = 0x0A + 0x05 SET_REG1 A = 0x0F flag:c = temp2.b u> 0xff - E ---------------- REG 0x000A = temp2 REG 0x0005 = E SUB1 0xFA = 0xFF - 0x05 CMP_UGT 0 = 0x000A > 0x00FA SET_FLAG c = 0 C = A ---------------- REG 0x000F = A SET_REG1 C = 0x0F A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0005 = DE ADD2 0x0006 = 0x0005 + 0x0001 SET_REG2 DE = 0x0006 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x0006 = E SUB1 0x04 = 0x0A - 0x06 SET_REG1 A = 0x04 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) REG 0x000A = temp0 REG 0x0006 = E SUB1 0x04 = 0x0A - 0x06 TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0006 = E SUB1 0x04 = 0x0A - 0x06 TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x000F = C SET_REG1 A = 0x0F temp2.b = A ---------------- REG 0x000F = A SET_REG1 temp2 = 0x0F A = A + E ---------------- REG 0x000F = A REG 0x0006 = E ADD1 0x15 = 0x0F + 0x06 SET_REG1 A = 0x15 flag:c = temp2.b u> 0xff - E ---------------- REG 0x000F = temp2 REG 0x0006 = E SUB1 0xF9 = 0xFF - 0x06 CMP_UGT 0 = 0x000F > 0x00F9 SET_FLAG c = 0 C = A ---------------- REG 0x0015 = A SET_REG1 C = 0x15 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0006 = DE ADD2 0x0007 = 0x0006 + 0x0001 SET_REG2 DE = 0x0007 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x0007 = E SUB1 0x03 = 0x0A - 0x07 SET_REG1 A = 0x03 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x000A = temp0 REG 0x0007 = E SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0007 = E SUB1 0x03 = 0x0A - 0x07 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0015 = C SET_REG1 A = 0x15 temp2.b = A ---------------- REG 0x0015 = A SET_REG1 temp2 = 0x15 A = A + E ---------------- REG 0x0015 = A REG 0x0007 = E ADD1 0x1C = 0x15 + 0x07 SET_REG1 A = 0x1C flag:c = temp2.b u> 0xff - E ---------------- REG 0x0015 = temp2 REG 0x0007 = E SUB1 0xF8 = 0xFF - 0x07 CMP_UGT 0 = 0x0015 > 0x00F8 SET_FLAG c = 0 C = A ---------------- REG 0x001C = A SET_REG1 C = 0x1C A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0007 = DE ADD2 0x0008 = 0x0007 + 0x0001 SET_REG2 DE = 0x0008 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x0008 = E SUB1 0x02 = 0x0A - 0x08 SET_REG1 A = 0x02 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0008 = E TEST_BIT 0 = bool(0x0008 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0008 = E TEST_BIT 0 = bool(0x0008 & 0x0080) REG 0x000A = temp0 REG 0x0008 = E SUB1 0x02 = 0x0A - 0x08 TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0008 = E SUB1 0x02 = 0x0A - 0x08 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x001C = C SET_REG1 A = 0x1C temp2.b = A ---------------- REG 0x001C = A SET_REG1 temp2 = 0x1C A = A + E ---------------- REG 0x001C = A REG 0x0008 = E ADD1 0x24 = 0x1C + 0x08 SET_REG1 A = 0x24 flag:c = temp2.b u> 0xff - E ---------------- REG 0x001C = temp2 REG 0x0008 = E SUB1 0xF7 = 0xFF - 0x08 CMP_UGT 0 = 0x001C > 0x00F7 SET_FLAG c = 0 C = A ---------------- REG 0x0024 = A SET_REG1 C = 0x24 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0008 = DE ADD2 0x0009 = 0x0008 + 0x0001 SET_REG2 DE = 0x0009 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x0009 = E SUB1 0x01 = 0x0A - 0x09 SET_REG1 A = 0x01 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0009 = E TEST_BIT 0 = bool(0x0009 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0009 = E TEST_BIT 0 = bool(0x0009 & 0x0080) REG 0x000A = temp0 REG 0x0009 = E SUB1 0x01 = 0x0A - 0x09 TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x0009 = E SUB1 0x01 = 0x0A - 0x09 TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0024 = C SET_REG1 A = 0x24 temp2.b = A ---------------- REG 0x0024 = A SET_REG1 temp2 = 0x24 A = A + E ---------------- REG 0x0024 = A REG 0x0009 = E ADD1 0x2D = 0x24 + 0x09 SET_REG1 A = 0x2D flag:c = temp2.b u> 0xff - E ---------------- REG 0x0024 = temp2 REG 0x0009 = E SUB1 0xF6 = 0xFF - 0x09 CMP_UGT 0 = 0x0024 > 0x00F6 SET_FLAG c = 0 C = A ---------------- REG 0x002D = A SET_REG1 C = 0x2D A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0009 = DE ADD2 0x000A = 0x0009 + 0x0001 SET_REG2 DE = 0x000A goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x000A = E SUB1 0x00 = 0x0A - 0x0A SET_REG1 A = 0x00 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000A = E TEST_BIT 0 = bool(0x000A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000A = E TEST_BIT 0 = bool(0x000A & 0x0080) REG 0x000A = temp0 REG 0x000A = E SUB1 0x00 = 0x0A - 0x0A TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x000A = E SUB1 0x00 = 0x0A - 0x0A TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x002D = C SET_REG1 A = 0x2D temp2.b = A ---------------- REG 0x002D = A SET_REG1 temp2 = 0x2D A = A + E ---------------- REG 0x002D = A REG 0x000A = E ADD1 0x37 = 0x2D + 0x0A SET_REG1 A = 0x37 flag:c = temp2.b u> 0xff - E ---------------- REG 0x002D = temp2 REG 0x000A = E SUB1 0xF5 = 0xFF - 0x0A CMP_UGT 0 = 0x002D > 0x00F5 SET_FLAG c = 0 C = A ---------------- REG 0x0037 = A SET_REG1 C = 0x37 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x000A = DE ADD2 0x000B = 0x000A + 0x0001 SET_REG2 DE = 0x000B goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 A = 0x0A temp0.b = A ---------------- REG 0x000A = A SET_REG1 temp0 = 0x0A A = A - E ---------------- REG 0x000A = A REG 0x000B = E SUB1 0xFF = 0x0A - 0x0B SET_REG1 A = 0xFF flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000B = E TEST_BIT 0 = bool(0x000B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000B = E TEST_BIT 0 = bool(0x000B & 0x0080) REG 0x000A = temp0 REG 0x000B = E SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x000A = temp0 REG 0x000B = E SUB1 0xFF = 0x0A - 0x0B TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x000A = temp0 TEST_BIT 0 = bool(0x000A & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 1 = vm_flags[s] L = C ---------------- REG 0x0037 = C SET_REG1 L = 0x37 H = B ---------------- REG 0x0000 = B SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m triangle_up(10) (55 is correct) BC = 0 ---------------- SET_REG2 BC = 0x0000 DE = 1 ---------------- SET_REG2 DE = 0x0001 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0001 = E SUB1 0x63 = 0x64 - 0x01 SET_REG1 A = 0x63 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x0064 = temp0 REG 0x0001 = E SUB1 0x63 = 0x64 - 0x01 TEST_BIT 0 = bool(0x0063 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0001 = E SUB1 0x63 = 0x64 - 0x01 TEST_BIT 0 = bool(0x0063 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0000 = C SET_REG1 A = 0x00 temp2.b = A ---------------- REG 0x0000 = A SET_REG1 temp2 = 0x00 A = A + E ---------------- REG 0x0000 = A REG 0x0001 = E ADD1 0x01 = 0x00 + 0x01 SET_REG1 A = 0x01 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0000 = temp2 REG 0x0001 = E SUB1 0xFE = 0xFF - 0x01 CMP_UGT 0 = 0x0000 > 0x00FE SET_FLAG c = 0 C = A ---------------- REG 0x0001 = A SET_REG1 C = 0x01 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0001 = DE ADD2 0x0002 = 0x0001 + 0x0001 SET_REG2 DE = 0x0002 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0002 = E SUB1 0x62 = 0x64 - 0x02 SET_REG1 A = 0x62 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x0064 = temp0 REG 0x0002 = E SUB1 0x62 = 0x64 - 0x02 TEST_BIT 0 = bool(0x0062 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0002 = E SUB1 0x62 = 0x64 - 0x02 TEST_BIT 0 = bool(0x0062 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0001 = C SET_REG1 A = 0x01 temp2.b = A ---------------- REG 0x0001 = A SET_REG1 temp2 = 0x01 A = A + E ---------------- REG 0x0001 = A REG 0x0002 = E ADD1 0x03 = 0x01 + 0x02 SET_REG1 A = 0x03 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0001 = temp2 REG 0x0002 = E SUB1 0xFD = 0xFF - 0x02 CMP_UGT 0 = 0x0001 > 0x00FD SET_FLAG c = 0 C = A ---------------- REG 0x0003 = A SET_REG1 C = 0x03 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0002 = DE ADD2 0x0003 = 0x0002 + 0x0001 SET_REG2 DE = 0x0003 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0003 = E SUB1 0x61 = 0x64 - 0x03 SET_REG1 A = 0x61 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x0064 = temp0 REG 0x0003 = E SUB1 0x61 = 0x64 - 0x03 TEST_BIT 0 = bool(0x0061 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0003 = E SUB1 0x61 = 0x64 - 0x03 TEST_BIT 0 = bool(0x0061 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0003 = C SET_REG1 A = 0x03 temp2.b = A ---------------- REG 0x0003 = A SET_REG1 temp2 = 0x03 A = A + E ---------------- REG 0x0003 = A REG 0x0003 = E ADD1 0x06 = 0x03 + 0x03 SET_REG1 A = 0x06 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0003 = temp2 REG 0x0003 = E SUB1 0xFC = 0xFF - 0x03 CMP_UGT 0 = 0x0003 > 0x00FC SET_FLAG c = 0 C = A ---------------- REG 0x0006 = A SET_REG1 C = 0x06 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0003 = DE ADD2 0x0004 = 0x0003 + 0x0001 SET_REG2 DE = 0x0004 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0004 = E SUB1 0x60 = 0x64 - 0x04 SET_REG1 A = 0x60 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x0064 = temp0 REG 0x0004 = E SUB1 0x60 = 0x64 - 0x04 TEST_BIT 0 = bool(0x0060 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0004 = E SUB1 0x60 = 0x64 - 0x04 TEST_BIT 0 = bool(0x0060 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0006 = C SET_REG1 A = 0x06 temp2.b = A ---------------- REG 0x0006 = A SET_REG1 temp2 = 0x06 A = A + E ---------------- REG 0x0006 = A REG 0x0004 = E ADD1 0x0A = 0x06 + 0x04 SET_REG1 A = 0x0A flag:c = temp2.b u> 0xff - E ---------------- REG 0x0006 = temp2 REG 0x0004 = E SUB1 0xFB = 0xFF - 0x04 CMP_UGT 0 = 0x0006 > 0x00FB SET_FLAG c = 0 C = A ---------------- REG 0x000A = A SET_REG1 C = 0x0A A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0004 = DE ADD2 0x0005 = 0x0004 + 0x0001 SET_REG2 DE = 0x0005 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0005 = E SUB1 0x5F = 0x64 - 0x05 SET_REG1 A = 0x5F flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) REG 0x0064 = temp0 REG 0x0005 = E SUB1 0x5F = 0x64 - 0x05 TEST_BIT 0 = bool(0x005F & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0005 = E SUB1 0x5F = 0x64 - 0x05 TEST_BIT 0 = bool(0x005F & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x000A = C SET_REG1 A = 0x0A temp2.b = A ---------------- REG 0x000A = A SET_REG1 temp2 = 0x0A A = A + E ---------------- REG 0x000A = A REG 0x0005 = E ADD1 0x0F = 0x0A + 0x05 SET_REG1 A = 0x0F flag:c = temp2.b u> 0xff - E ---------------- REG 0x000A = temp2 REG 0x0005 = E SUB1 0xFA = 0xFF - 0x05 CMP_UGT 0 = 0x000A > 0x00FA SET_FLAG c = 0 C = A ---------------- REG 0x000F = A SET_REG1 C = 0x0F A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0005 = DE ADD2 0x0006 = 0x0005 + 0x0001 SET_REG2 DE = 0x0006 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0006 = E SUB1 0x5E = 0x64 - 0x06 SET_REG1 A = 0x5E flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) REG 0x0064 = temp0 REG 0x0006 = E SUB1 0x5E = 0x64 - 0x06 TEST_BIT 0 = bool(0x005E & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0006 = E SUB1 0x5E = 0x64 - 0x06 TEST_BIT 0 = bool(0x005E & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x000F = C SET_REG1 A = 0x0F temp2.b = A ---------------- REG 0x000F = A SET_REG1 temp2 = 0x0F A = A + E ---------------- REG 0x000F = A REG 0x0006 = E ADD1 0x15 = 0x0F + 0x06 SET_REG1 A = 0x15 flag:c = temp2.b u> 0xff - E ---------------- REG 0x000F = temp2 REG 0x0006 = E SUB1 0xF9 = 0xFF - 0x06 CMP_UGT 0 = 0x000F > 0x00F9 SET_FLAG c = 0 C = A ---------------- REG 0x0015 = A SET_REG1 C = 0x15 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0006 = DE ADD2 0x0007 = 0x0006 + 0x0001 SET_REG2 DE = 0x0007 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0007 = E SUB1 0x5D = 0x64 - 0x07 SET_REG1 A = 0x5D flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x0064 = temp0 REG 0x0007 = E SUB1 0x5D = 0x64 - 0x07 TEST_BIT 0 = bool(0x005D & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0007 = E SUB1 0x5D = 0x64 - 0x07 TEST_BIT 0 = bool(0x005D & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0015 = C SET_REG1 A = 0x15 temp2.b = A ---------------- REG 0x0015 = A SET_REG1 temp2 = 0x15 A = A + E ---------------- REG 0x0015 = A REG 0x0007 = E ADD1 0x1C = 0x15 + 0x07 SET_REG1 A = 0x1C flag:c = temp2.b u> 0xff - E ---------------- REG 0x0015 = temp2 REG 0x0007 = E SUB1 0xF8 = 0xFF - 0x07 CMP_UGT 0 = 0x0015 > 0x00F8 SET_FLAG c = 0 C = A ---------------- REG 0x001C = A SET_REG1 C = 0x1C A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0007 = DE ADD2 0x0008 = 0x0007 + 0x0001 SET_REG2 DE = 0x0008 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0008 = E SUB1 0x5C = 0x64 - 0x08 SET_REG1 A = 0x5C flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0008 = E TEST_BIT 0 = bool(0x0008 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0008 = E TEST_BIT 0 = bool(0x0008 & 0x0080) REG 0x0064 = temp0 REG 0x0008 = E SUB1 0x5C = 0x64 - 0x08 TEST_BIT 0 = bool(0x005C & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0008 = E SUB1 0x5C = 0x64 - 0x08 TEST_BIT 0 = bool(0x005C & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x001C = C SET_REG1 A = 0x1C temp2.b = A ---------------- REG 0x001C = A SET_REG1 temp2 = 0x1C A = A + E ---------------- REG 0x001C = A REG 0x0008 = E ADD1 0x24 = 0x1C + 0x08 SET_REG1 A = 0x24 flag:c = temp2.b u> 0xff - E ---------------- REG 0x001C = temp2 REG 0x0008 = E SUB1 0xF7 = 0xFF - 0x08 CMP_UGT 0 = 0x001C > 0x00F7 SET_FLAG c = 0 C = A ---------------- REG 0x0024 = A SET_REG1 C = 0x24 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0008 = DE ADD2 0x0009 = 0x0008 + 0x0001 SET_REG2 DE = 0x0009 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0009 = E SUB1 0x5B = 0x64 - 0x09 SET_REG1 A = 0x5B flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0009 = E TEST_BIT 0 = bool(0x0009 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0009 = E TEST_BIT 0 = bool(0x0009 & 0x0080) REG 0x0064 = temp0 REG 0x0009 = E SUB1 0x5B = 0x64 - 0x09 TEST_BIT 0 = bool(0x005B & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0009 = E SUB1 0x5B = 0x64 - 0x09 TEST_BIT 0 = bool(0x005B & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0024 = C SET_REG1 A = 0x24 temp2.b = A ---------------- REG 0x0024 = A SET_REG1 temp2 = 0x24 A = A + E ---------------- REG 0x0024 = A REG 0x0009 = E ADD1 0x2D = 0x24 + 0x09 SET_REG1 A = 0x2D flag:c = temp2.b u> 0xff - E ---------------- REG 0x0024 = temp2 REG 0x0009 = E SUB1 0xF6 = 0xFF - 0x09 CMP_UGT 0 = 0x0024 > 0x00F6 SET_FLAG c = 0 C = A ---------------- REG 0x002D = A SET_REG1 C = 0x2D A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0009 = DE ADD2 0x000A = 0x0009 + 0x0001 SET_REG2 DE = 0x000A goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x000A = E SUB1 0x5A = 0x64 - 0x0A SET_REG1 A = 0x5A flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000A = E TEST_BIT 0 = bool(0x000A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000A = E TEST_BIT 0 = bool(0x000A & 0x0080) REG 0x0064 = temp0 REG 0x000A = E SUB1 0x5A = 0x64 - 0x0A TEST_BIT 0 = bool(0x005A & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x000A = E SUB1 0x5A = 0x64 - 0x0A TEST_BIT 0 = bool(0x005A & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x002D = C SET_REG1 A = 0x2D temp2.b = A ---------------- REG 0x002D = A SET_REG1 temp2 = 0x2D A = A + E ---------------- REG 0x002D = A REG 0x000A = E ADD1 0x37 = 0x2D + 0x0A SET_REG1 A = 0x37 flag:c = temp2.b u> 0xff - E ---------------- REG 0x002D = temp2 REG 0x000A = E SUB1 0xF5 = 0xFF - 0x0A CMP_UGT 0 = 0x002D > 0x00F5 SET_FLAG c = 0 C = A ---------------- REG 0x0037 = A SET_REG1 C = 0x37 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x000A = DE ADD2 0x000B = 0x000A + 0x0001 SET_REG2 DE = 0x000B goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x000B = E SUB1 0x59 = 0x64 - 0x0B SET_REG1 A = 0x59 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000B = E TEST_BIT 0 = bool(0x000B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000B = E TEST_BIT 0 = bool(0x000B & 0x0080) REG 0x0064 = temp0 REG 0x000B = E SUB1 0x59 = 0x64 - 0x0B TEST_BIT 0 = bool(0x0059 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x000B = E SUB1 0x59 = 0x64 - 0x0B TEST_BIT 0 = bool(0x0059 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0037 = C SET_REG1 A = 0x37 temp2.b = A ---------------- REG 0x0037 = A SET_REG1 temp2 = 0x37 A = A + E ---------------- REG 0x0037 = A REG 0x000B = E ADD1 0x42 = 0x37 + 0x0B SET_REG1 A = 0x42 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0037 = temp2 REG 0x000B = E SUB1 0xF4 = 0xFF - 0x0B CMP_UGT 0 = 0x0037 > 0x00F4 SET_FLAG c = 0 C = A ---------------- REG 0x0042 = A SET_REG1 C = 0x42 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x000B = DE ADD2 0x000C = 0x000B + 0x0001 SET_REG2 DE = 0x000C goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x000C = E SUB1 0x58 = 0x64 - 0x0C SET_REG1 A = 0x58 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000C = E TEST_BIT 0 = bool(0x000C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000C = E TEST_BIT 0 = bool(0x000C & 0x0080) REG 0x0064 = temp0 REG 0x000C = E SUB1 0x58 = 0x64 - 0x0C TEST_BIT 0 = bool(0x0058 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x000C = E SUB1 0x58 = 0x64 - 0x0C TEST_BIT 0 = bool(0x0058 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0042 = C SET_REG1 A = 0x42 temp2.b = A ---------------- REG 0x0042 = A SET_REG1 temp2 = 0x42 A = A + E ---------------- REG 0x0042 = A REG 0x000C = E ADD1 0x4E = 0x42 + 0x0C SET_REG1 A = 0x4E flag:c = temp2.b u> 0xff - E ---------------- REG 0x0042 = temp2 REG 0x000C = E SUB1 0xF3 = 0xFF - 0x0C CMP_UGT 0 = 0x0042 > 0x00F3 SET_FLAG c = 0 C = A ---------------- REG 0x004E = A SET_REG1 C = 0x4E A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x000C = DE ADD2 0x000D = 0x000C + 0x0001 SET_REG2 DE = 0x000D goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x000D = E SUB1 0x57 = 0x64 - 0x0D SET_REG1 A = 0x57 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000D = E TEST_BIT 0 = bool(0x000D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000D = E TEST_BIT 0 = bool(0x000D & 0x0080) REG 0x0064 = temp0 REG 0x000D = E SUB1 0x57 = 0x64 - 0x0D TEST_BIT 0 = bool(0x0057 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x000D = E SUB1 0x57 = 0x64 - 0x0D TEST_BIT 0 = bool(0x0057 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x004E = C SET_REG1 A = 0x4E temp2.b = A ---------------- REG 0x004E = A SET_REG1 temp2 = 0x4E A = A + E ---------------- REG 0x004E = A REG 0x000D = E ADD1 0x5B = 0x4E + 0x0D SET_REG1 A = 0x5B flag:c = temp2.b u> 0xff - E ---------------- REG 0x004E = temp2 REG 0x000D = E SUB1 0xF2 = 0xFF - 0x0D CMP_UGT 0 = 0x004E > 0x00F2 SET_FLAG c = 0 C = A ---------------- REG 0x005B = A SET_REG1 C = 0x5B A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x000D = DE ADD2 0x000E = 0x000D + 0x0001 SET_REG2 DE = 0x000E goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x000E = E SUB1 0x56 = 0x64 - 0x0E SET_REG1 A = 0x56 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000E = E TEST_BIT 0 = bool(0x000E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000E = E TEST_BIT 0 = bool(0x000E & 0x0080) REG 0x0064 = temp0 REG 0x000E = E SUB1 0x56 = 0x64 - 0x0E TEST_BIT 0 = bool(0x0056 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x000E = E SUB1 0x56 = 0x64 - 0x0E TEST_BIT 0 = bool(0x0056 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x005B = C SET_REG1 A = 0x5B temp2.b = A ---------------- REG 0x005B = A SET_REG1 temp2 = 0x5B A = A + E ---------------- REG 0x005B = A REG 0x000E = E ADD1 0x69 = 0x5B + 0x0E SET_REG1 A = 0x69 flag:c = temp2.b u> 0xff - E ---------------- REG 0x005B = temp2 REG 0x000E = E SUB1 0xF1 = 0xFF - 0x0E CMP_UGT 0 = 0x005B > 0x00F1 SET_FLAG c = 0 C = A ---------------- REG 0x0069 = A SET_REG1 C = 0x69 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x000E = DE ADD2 0x000F = 0x000E + 0x0001 SET_REG2 DE = 0x000F goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x000F = E SUB1 0x55 = 0x64 - 0x0F SET_REG1 A = 0x55 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000F = E TEST_BIT 0 = bool(0x000F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000F = E TEST_BIT 0 = bool(0x000F & 0x0080) REG 0x0064 = temp0 REG 0x000F = E SUB1 0x55 = 0x64 - 0x0F TEST_BIT 0 = bool(0x0055 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x000F = E SUB1 0x55 = 0x64 - 0x0F TEST_BIT 0 = bool(0x0055 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0069 = C SET_REG1 A = 0x69 temp2.b = A ---------------- REG 0x0069 = A SET_REG1 temp2 = 0x69 A = A + E ---------------- REG 0x0069 = A REG 0x000F = E ADD1 0x78 = 0x69 + 0x0F SET_REG1 A = 0x78 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0069 = temp2 REG 0x000F = E SUB1 0xF0 = 0xFF - 0x0F CMP_UGT 0 = 0x0069 > 0x00F0 SET_FLAG c = 0 C = A ---------------- REG 0x0078 = A SET_REG1 C = 0x78 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x000F = DE ADD2 0x0010 = 0x000F + 0x0001 SET_REG2 DE = 0x0010 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0010 = E SUB1 0x54 = 0x64 - 0x10 SET_REG1 A = 0x54 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0010 = E TEST_BIT 0 = bool(0x0010 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0010 = E TEST_BIT 0 = bool(0x0010 & 0x0080) REG 0x0064 = temp0 REG 0x0010 = E SUB1 0x54 = 0x64 - 0x10 TEST_BIT 0 = bool(0x0054 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0010 = E SUB1 0x54 = 0x64 - 0x10 TEST_BIT 0 = bool(0x0054 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0078 = C SET_REG1 A = 0x78 temp2.b = A ---------------- REG 0x0078 = A SET_REG1 temp2 = 0x78 A = A + E ---------------- REG 0x0078 = A REG 0x0010 = E ADD1 0x88 = 0x78 + 0x10 SET_REG1 A = 0x88 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0078 = temp2 REG 0x0010 = E SUB1 0xEF = 0xFF - 0x10 CMP_UGT 0 = 0x0078 > 0x00EF SET_FLAG c = 0 C = A ---------------- REG 0x0088 = A SET_REG1 C = 0x88 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0010 = DE ADD2 0x0011 = 0x0010 + 0x0001 SET_REG2 DE = 0x0011 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0011 = E SUB1 0x53 = 0x64 - 0x11 SET_REG1 A = 0x53 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0011 = E TEST_BIT 0 = bool(0x0011 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0011 = E TEST_BIT 0 = bool(0x0011 & 0x0080) REG 0x0064 = temp0 REG 0x0011 = E SUB1 0x53 = 0x64 - 0x11 TEST_BIT 0 = bool(0x0053 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0011 = E SUB1 0x53 = 0x64 - 0x11 TEST_BIT 0 = bool(0x0053 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0088 = C SET_REG1 A = 0x88 temp2.b = A ---------------- REG 0x0088 = A SET_REG1 temp2 = 0x88 A = A + E ---------------- REG 0x0088 = A REG 0x0011 = E ADD1 0x99 = 0x88 + 0x11 SET_REG1 A = 0x99 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0088 = temp2 REG 0x0011 = E SUB1 0xEE = 0xFF - 0x11 CMP_UGT 0 = 0x0088 > 0x00EE SET_FLAG c = 0 C = A ---------------- REG 0x0099 = A SET_REG1 C = 0x99 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0011 = DE ADD2 0x0012 = 0x0011 + 0x0001 SET_REG2 DE = 0x0012 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0012 = E SUB1 0x52 = 0x64 - 0x12 SET_REG1 A = 0x52 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0012 = E TEST_BIT 0 = bool(0x0012 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0012 = E TEST_BIT 0 = bool(0x0012 & 0x0080) REG 0x0064 = temp0 REG 0x0012 = E SUB1 0x52 = 0x64 - 0x12 TEST_BIT 0 = bool(0x0052 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0012 = E SUB1 0x52 = 0x64 - 0x12 TEST_BIT 0 = bool(0x0052 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0099 = C SET_REG1 A = 0x99 temp2.b = A ---------------- REG 0x0099 = A SET_REG1 temp2 = 0x99 A = A + E ---------------- REG 0x0099 = A REG 0x0012 = E ADD1 0xAB = 0x99 + 0x12 SET_REG1 A = 0xAB flag:c = temp2.b u> 0xff - E ---------------- REG 0x0099 = temp2 REG 0x0012 = E SUB1 0xED = 0xFF - 0x12 CMP_UGT 0 = 0x0099 > 0x00ED SET_FLAG c = 0 C = A ---------------- REG 0x00AB = A SET_REG1 C = 0xAB A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0012 = DE ADD2 0x0013 = 0x0012 + 0x0001 SET_REG2 DE = 0x0013 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0013 = E SUB1 0x51 = 0x64 - 0x13 SET_REG1 A = 0x51 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0013 = E TEST_BIT 0 = bool(0x0013 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0013 = E TEST_BIT 0 = bool(0x0013 & 0x0080) REG 0x0064 = temp0 REG 0x0013 = E SUB1 0x51 = 0x64 - 0x13 TEST_BIT 0 = bool(0x0051 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0013 = E SUB1 0x51 = 0x64 - 0x13 TEST_BIT 0 = bool(0x0051 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00AB = C SET_REG1 A = 0xAB temp2.b = A ---------------- REG 0x00AB = A SET_REG1 temp2 = 0xAB A = A + E ---------------- REG 0x00AB = A REG 0x0013 = E ADD1 0xBE = 0xAB + 0x13 SET_REG1 A = 0xBE flag:c = temp2.b u> 0xff - E ---------------- REG 0x00AB = temp2 REG 0x0013 = E SUB1 0xEC = 0xFF - 0x13 CMP_UGT 0 = 0x00AB > 0x00EC SET_FLAG c = 0 C = A ---------------- REG 0x00BE = A SET_REG1 C = 0xBE A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0013 = DE ADD2 0x0014 = 0x0013 + 0x0001 SET_REG2 DE = 0x0014 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0014 = E SUB1 0x50 = 0x64 - 0x14 SET_REG1 A = 0x50 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0014 = E TEST_BIT 0 = bool(0x0014 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0014 = E TEST_BIT 0 = bool(0x0014 & 0x0080) REG 0x0064 = temp0 REG 0x0014 = E SUB1 0x50 = 0x64 - 0x14 TEST_BIT 0 = bool(0x0050 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0014 = E SUB1 0x50 = 0x64 - 0x14 TEST_BIT 0 = bool(0x0050 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00BE = C SET_REG1 A = 0xBE temp2.b = A ---------------- REG 0x00BE = A SET_REG1 temp2 = 0xBE A = A + E ---------------- REG 0x00BE = A REG 0x0014 = E ADD1 0xD2 = 0xBE + 0x14 SET_REG1 A = 0xD2 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00BE = temp2 REG 0x0014 = E SUB1 0xEB = 0xFF - 0x14 CMP_UGT 0 = 0x00BE > 0x00EB SET_FLAG c = 0 C = A ---------------- REG 0x00D2 = A SET_REG1 C = 0xD2 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0014 = DE ADD2 0x0015 = 0x0014 + 0x0001 SET_REG2 DE = 0x0015 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0015 = E SUB1 0x4F = 0x64 - 0x15 SET_REG1 A = 0x4F flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0015 = E TEST_BIT 0 = bool(0x0015 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0015 = E TEST_BIT 0 = bool(0x0015 & 0x0080) REG 0x0064 = temp0 REG 0x0015 = E SUB1 0x4F = 0x64 - 0x15 TEST_BIT 0 = bool(0x004F & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0015 = E SUB1 0x4F = 0x64 - 0x15 TEST_BIT 0 = bool(0x004F & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00D2 = C SET_REG1 A = 0xD2 temp2.b = A ---------------- REG 0x00D2 = A SET_REG1 temp2 = 0xD2 A = A + E ---------------- REG 0x00D2 = A REG 0x0015 = E ADD1 0xE7 = 0xD2 + 0x15 SET_REG1 A = 0xE7 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00D2 = temp2 REG 0x0015 = E SUB1 0xEA = 0xFF - 0x15 CMP_UGT 0 = 0x00D2 > 0x00EA SET_FLAG c = 0 C = A ---------------- REG 0x00E7 = A SET_REG1 C = 0xE7 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0015 = DE ADD2 0x0016 = 0x0015 + 0x0001 SET_REG2 DE = 0x0016 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0016 = E SUB1 0x4E = 0x64 - 0x16 SET_REG1 A = 0x4E flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0016 = E TEST_BIT 0 = bool(0x0016 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0016 = E TEST_BIT 0 = bool(0x0016 & 0x0080) REG 0x0064 = temp0 REG 0x0016 = E SUB1 0x4E = 0x64 - 0x16 TEST_BIT 0 = bool(0x004E & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0016 = E SUB1 0x4E = 0x64 - 0x16 TEST_BIT 0 = bool(0x004E & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00E7 = C SET_REG1 A = 0xE7 temp2.b = A ---------------- REG 0x00E7 = A SET_REG1 temp2 = 0xE7 A = A + E ---------------- REG 0x00E7 = A REG 0x0016 = E ADD1 0xFD = 0xE7 + 0x16 SET_REG1 A = 0xFD flag:c = temp2.b u> 0xff - E ---------------- REG 0x00E7 = temp2 REG 0x0016 = E SUB1 0xE9 = 0xFF - 0x16 CMP_UGT 0 = 0x00E7 > 0x00E9 SET_FLAG c = 0 C = A ---------------- REG 0x00FD = A SET_REG1 C = 0xFD A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE + 1 ---------------- REG 0x0016 = DE ADD2 0x0017 = 0x0016 + 0x0001 SET_REG2 DE = 0x0017 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0017 = E SUB1 0x4D = 0x64 - 0x17 SET_REG1 A = 0x4D flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0017 = E TEST_BIT 0 = bool(0x0017 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0017 = E TEST_BIT 0 = bool(0x0017 & 0x0080) REG 0x0064 = temp0 REG 0x0017 = E SUB1 0x4D = 0x64 - 0x17 TEST_BIT 0 = bool(0x004D & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0017 = E SUB1 0x4D = 0x64 - 0x17 TEST_BIT 0 = bool(0x004D & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00FD = C SET_REG1 A = 0xFD temp2.b = A ---------------- REG 0x00FD = A SET_REG1 temp2 = 0xFD A = A + E ---------------- REG 0x00FD = A REG 0x0017 = E ADD1 0x14 = 0xFD + 0x17 SET_REG1 A = 0x14 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00FD = temp2 REG 0x0017 = E SUB1 0xE8 = 0xFF - 0x17 CMP_UGT 1 = 0x00FD > 0x00E8 SET_FLAG c = 1 C = A ---------------- REG 0x0014 = A SET_REG1 C = 0x14 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0001 = 0x0000 + 0x0000 + 1 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE + 1 ---------------- REG 0x0017 = DE ADD2 0x0018 = 0x0017 + 0x0001 SET_REG2 DE = 0x0018 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0018 = E SUB1 0x4C = 0x64 - 0x18 SET_REG1 A = 0x4C flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0018 = E TEST_BIT 0 = bool(0x0018 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0018 = E TEST_BIT 0 = bool(0x0018 & 0x0080) REG 0x0064 = temp0 REG 0x0018 = E SUB1 0x4C = 0x64 - 0x18 TEST_BIT 0 = bool(0x004C & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0018 = E SUB1 0x4C = 0x64 - 0x18 TEST_BIT 0 = bool(0x004C & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0014 = C SET_REG1 A = 0x14 temp2.b = A ---------------- REG 0x0014 = A SET_REG1 temp2 = 0x14 A = A + E ---------------- REG 0x0014 = A REG 0x0018 = E ADD1 0x2C = 0x14 + 0x18 SET_REG1 A = 0x2C flag:c = temp2.b u> 0xff - E ---------------- REG 0x0014 = temp2 REG 0x0018 = E SUB1 0xE7 = 0xFF - 0x18 CMP_UGT 0 = 0x0014 > 0x00E7 SET_FLAG c = 0 C = A ---------------- REG 0x002C = A SET_REG1 C = 0x2C A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0001 = 0x0001 + 0x0000 + 0 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE + 1 ---------------- REG 0x0018 = DE ADD2 0x0019 = 0x0018 + 0x0001 SET_REG2 DE = 0x0019 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0019 = E SUB1 0x4B = 0x64 - 0x19 SET_REG1 A = 0x4B flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0019 = E TEST_BIT 0 = bool(0x0019 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0019 = E TEST_BIT 0 = bool(0x0019 & 0x0080) REG 0x0064 = temp0 REG 0x0019 = E SUB1 0x4B = 0x64 - 0x19 TEST_BIT 0 = bool(0x004B & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0019 = E SUB1 0x4B = 0x64 - 0x19 TEST_BIT 0 = bool(0x004B & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x002C = C SET_REG1 A = 0x2C temp2.b = A ---------------- REG 0x002C = A SET_REG1 temp2 = 0x2C A = A + E ---------------- REG 0x002C = A REG 0x0019 = E ADD1 0x45 = 0x2C + 0x19 SET_REG1 A = 0x45 flag:c = temp2.b u> 0xff - E ---------------- REG 0x002C = temp2 REG 0x0019 = E SUB1 0xE6 = 0xFF - 0x19 CMP_UGT 0 = 0x002C > 0x00E6 SET_FLAG c = 0 C = A ---------------- REG 0x0045 = A SET_REG1 C = 0x45 A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0001 = 0x0001 + 0x0000 + 0 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE + 1 ---------------- REG 0x0019 = DE ADD2 0x001A = 0x0019 + 0x0001 SET_REG2 DE = 0x001A goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x001A = E SUB1 0x4A = 0x64 - 0x1A SET_REG1 A = 0x4A flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001A = E TEST_BIT 0 = bool(0x001A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001A = E TEST_BIT 0 = bool(0x001A & 0x0080) REG 0x0064 = temp0 REG 0x001A = E SUB1 0x4A = 0x64 - 0x1A TEST_BIT 0 = bool(0x004A & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x001A = E SUB1 0x4A = 0x64 - 0x1A TEST_BIT 0 = bool(0x004A & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0045 = C SET_REG1 A = 0x45 temp2.b = A ---------------- REG 0x0045 = A SET_REG1 temp2 = 0x45 A = A + E ---------------- REG 0x0045 = A REG 0x001A = E ADD1 0x5F = 0x45 + 0x1A SET_REG1 A = 0x5F flag:c = temp2.b u> 0xff - E ---------------- REG 0x0045 = temp2 REG 0x001A = E SUB1 0xE5 = 0xFF - 0x1A CMP_UGT 0 = 0x0045 > 0x00E5 SET_FLAG c = 0 C = A ---------------- REG 0x005F = A SET_REG1 C = 0x5F A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0001 = 0x0001 + 0x0000 + 0 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE + 1 ---------------- REG 0x001A = DE ADD2 0x001B = 0x001A + 0x0001 SET_REG2 DE = 0x001B goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x001B = E SUB1 0x49 = 0x64 - 0x1B SET_REG1 A = 0x49 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001B = E TEST_BIT 0 = bool(0x001B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001B = E TEST_BIT 0 = bool(0x001B & 0x0080) REG 0x0064 = temp0 REG 0x001B = E SUB1 0x49 = 0x64 - 0x1B TEST_BIT 0 = bool(0x0049 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x001B = E SUB1 0x49 = 0x64 - 0x1B TEST_BIT 0 = bool(0x0049 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x005F = C SET_REG1 A = 0x5F temp2.b = A ---------------- REG 0x005F = A SET_REG1 temp2 = 0x5F A = A + E ---------------- REG 0x005F = A REG 0x001B = E ADD1 0x7A = 0x5F + 0x1B SET_REG1 A = 0x7A flag:c = temp2.b u> 0xff - E ---------------- REG 0x005F = temp2 REG 0x001B = E SUB1 0xE4 = 0xFF - 0x1B CMP_UGT 0 = 0x005F > 0x00E4 SET_FLAG c = 0 C = A ---------------- REG 0x007A = A SET_REG1 C = 0x7A A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0001 = 0x0001 + 0x0000 + 0 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE + 1 ---------------- REG 0x001B = DE ADD2 0x001C = 0x001B + 0x0001 SET_REG2 DE = 0x001C goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x001C = E SUB1 0x48 = 0x64 - 0x1C SET_REG1 A = 0x48 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001C = E TEST_BIT 0 = bool(0x001C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001C = E TEST_BIT 0 = bool(0x001C & 0x0080) REG 0x0064 = temp0 REG 0x001C = E SUB1 0x48 = 0x64 - 0x1C TEST_BIT 0 = bool(0x0048 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x001C = E SUB1 0x48 = 0x64 - 0x1C TEST_BIT 0 = bool(0x0048 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x007A = C SET_REG1 A = 0x7A temp2.b = A ---------------- REG 0x007A = A SET_REG1 temp2 = 0x7A A = A + E ---------------- REG 0x007A = A REG 0x001C = E ADD1 0x96 = 0x7A + 0x1C SET_REG1 A = 0x96 flag:c = temp2.b u> 0xff - E ---------------- REG 0x007A = temp2 REG 0x001C = E SUB1 0xE3 = 0xFF - 0x1C CMP_UGT 0 = 0x007A > 0x00E3 SET_FLAG c = 0 C = A ---------------- REG 0x0096 = A SET_REG1 C = 0x96 A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0001 = 0x0001 + 0x0000 + 0 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE + 1 ---------------- REG 0x001C = DE ADD2 0x001D = 0x001C + 0x0001 SET_REG2 DE = 0x001D goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x001D = E SUB1 0x47 = 0x64 - 0x1D SET_REG1 A = 0x47 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001D = E TEST_BIT 0 = bool(0x001D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001D = E TEST_BIT 0 = bool(0x001D & 0x0080) REG 0x0064 = temp0 REG 0x001D = E SUB1 0x47 = 0x64 - 0x1D TEST_BIT 0 = bool(0x0047 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x001D = E SUB1 0x47 = 0x64 - 0x1D TEST_BIT 0 = bool(0x0047 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0096 = C SET_REG1 A = 0x96 temp2.b = A ---------------- REG 0x0096 = A SET_REG1 temp2 = 0x96 A = A + E ---------------- REG 0x0096 = A REG 0x001D = E ADD1 0xB3 = 0x96 + 0x1D SET_REG1 A = 0xB3 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0096 = temp2 REG 0x001D = E SUB1 0xE2 = 0xFF - 0x1D CMP_UGT 0 = 0x0096 > 0x00E2 SET_FLAG c = 0 C = A ---------------- REG 0x00B3 = A SET_REG1 C = 0xB3 A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0001 = 0x0001 + 0x0000 + 0 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE + 1 ---------------- REG 0x001D = DE ADD2 0x001E = 0x001D + 0x0001 SET_REG2 DE = 0x001E goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x001E = E SUB1 0x46 = 0x64 - 0x1E SET_REG1 A = 0x46 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001E = E TEST_BIT 0 = bool(0x001E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001E = E TEST_BIT 0 = bool(0x001E & 0x0080) REG 0x0064 = temp0 REG 0x001E = E SUB1 0x46 = 0x64 - 0x1E TEST_BIT 0 = bool(0x0046 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x001E = E SUB1 0x46 = 0x64 - 0x1E TEST_BIT 0 = bool(0x0046 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00B3 = C SET_REG1 A = 0xB3 temp2.b = A ---------------- REG 0x00B3 = A SET_REG1 temp2 = 0xB3 A = A + E ---------------- REG 0x00B3 = A REG 0x001E = E ADD1 0xD1 = 0xB3 + 0x1E SET_REG1 A = 0xD1 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00B3 = temp2 REG 0x001E = E SUB1 0xE1 = 0xFF - 0x1E CMP_UGT 0 = 0x00B3 > 0x00E1 SET_FLAG c = 0 C = A ---------------- REG 0x00D1 = A SET_REG1 C = 0xD1 A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0001 = 0x0001 + 0x0000 + 0 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE + 1 ---------------- REG 0x001E = DE ADD2 0x001F = 0x001E + 0x0001 SET_REG2 DE = 0x001F goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x001F = E SUB1 0x45 = 0x64 - 0x1F SET_REG1 A = 0x45 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001F = E TEST_BIT 0 = bool(0x001F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001F = E TEST_BIT 0 = bool(0x001F & 0x0080) REG 0x0064 = temp0 REG 0x001F = E SUB1 0x45 = 0x64 - 0x1F TEST_BIT 0 = bool(0x0045 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x001F = E SUB1 0x45 = 0x64 - 0x1F TEST_BIT 0 = bool(0x0045 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00D1 = C SET_REG1 A = 0xD1 temp2.b = A ---------------- REG 0x00D1 = A SET_REG1 temp2 = 0xD1 A = A + E ---------------- REG 0x00D1 = A REG 0x001F = E ADD1 0xF0 = 0xD1 + 0x1F SET_REG1 A = 0xF0 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00D1 = temp2 REG 0x001F = E SUB1 0xE0 = 0xFF - 0x1F CMP_UGT 0 = 0x00D1 > 0x00E0 SET_FLAG c = 0 C = A ---------------- REG 0x00F0 = A SET_REG1 C = 0xF0 A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0001 = 0x0001 + 0x0000 + 0 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE + 1 ---------------- REG 0x001F = DE ADD2 0x0020 = 0x001F + 0x0001 SET_REG2 DE = 0x0020 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0020 = E SUB1 0x44 = 0x64 - 0x20 SET_REG1 A = 0x44 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0020 = E TEST_BIT 0 = bool(0x0020 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0020 = E TEST_BIT 0 = bool(0x0020 & 0x0080) REG 0x0064 = temp0 REG 0x0020 = E SUB1 0x44 = 0x64 - 0x20 TEST_BIT 0 = bool(0x0044 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0020 = E SUB1 0x44 = 0x64 - 0x20 TEST_BIT 0 = bool(0x0044 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00F0 = C SET_REG1 A = 0xF0 temp2.b = A ---------------- REG 0x00F0 = A SET_REG1 temp2 = 0xF0 A = A + E ---------------- REG 0x00F0 = A REG 0x0020 = E ADD1 0x10 = 0xF0 + 0x20 SET_REG1 A = 0x10 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00F0 = temp2 REG 0x0020 = E SUB1 0xDF = 0xFF - 0x20 CMP_UGT 1 = 0x00F0 > 0x00DF SET_FLAG c = 1 C = A ---------------- REG 0x0010 = A SET_REG1 C = 0x10 A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0002 = 0x0001 + 0x0000 + 1 SET_REG1 A = 0x02 B = A ---------------- REG 0x0002 = A SET_REG1 B = 0x02 DE = DE + 1 ---------------- REG 0x0020 = DE ADD2 0x0021 = 0x0020 + 0x0001 SET_REG2 DE = 0x0021 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0021 = E SUB1 0x43 = 0x64 - 0x21 SET_REG1 A = 0x43 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0021 = E TEST_BIT 0 = bool(0x0021 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0021 = E TEST_BIT 0 = bool(0x0021 & 0x0080) REG 0x0064 = temp0 REG 0x0021 = E SUB1 0x43 = 0x64 - 0x21 TEST_BIT 0 = bool(0x0043 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0021 = E SUB1 0x43 = 0x64 - 0x21 TEST_BIT 0 = bool(0x0043 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0010 = C SET_REG1 A = 0x10 temp2.b = A ---------------- REG 0x0010 = A SET_REG1 temp2 = 0x10 A = A + E ---------------- REG 0x0010 = A REG 0x0021 = E ADD1 0x31 = 0x10 + 0x21 SET_REG1 A = 0x31 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0010 = temp2 REG 0x0021 = E SUB1 0xDE = 0xFF - 0x21 CMP_UGT 0 = 0x0010 > 0x00DE SET_FLAG c = 0 C = A ---------------- REG 0x0031 = A SET_REG1 C = 0x31 A = B ---------------- REG 0x0002 = B SET_REG1 A = 0x02 A = adc.b(A, D, flag:c) ---------------- REG 0x0002 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0002 = 0x0002 + 0x0000 + 0 SET_REG1 A = 0x02 B = A ---------------- REG 0x0002 = A SET_REG1 B = 0x02 DE = DE + 1 ---------------- REG 0x0021 = DE ADD2 0x0022 = 0x0021 + 0x0001 SET_REG2 DE = 0x0022 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0022 = E SUB1 0x42 = 0x64 - 0x22 SET_REG1 A = 0x42 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0022 = E TEST_BIT 0 = bool(0x0022 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0022 = E TEST_BIT 0 = bool(0x0022 & 0x0080) REG 0x0064 = temp0 REG 0x0022 = E SUB1 0x42 = 0x64 - 0x22 TEST_BIT 0 = bool(0x0042 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0022 = E SUB1 0x42 = 0x64 - 0x22 TEST_BIT 0 = bool(0x0042 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0031 = C SET_REG1 A = 0x31 temp2.b = A ---------------- REG 0x0031 = A SET_REG1 temp2 = 0x31 A = A + E ---------------- REG 0x0031 = A REG 0x0022 = E ADD1 0x53 = 0x31 + 0x22 SET_REG1 A = 0x53 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0031 = temp2 REG 0x0022 = E SUB1 0xDD = 0xFF - 0x22 CMP_UGT 0 = 0x0031 > 0x00DD SET_FLAG c = 0 C = A ---------------- REG 0x0053 = A SET_REG1 C = 0x53 A = B ---------------- REG 0x0002 = B SET_REG1 A = 0x02 A = adc.b(A, D, flag:c) ---------------- REG 0x0002 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0002 = 0x0002 + 0x0000 + 0 SET_REG1 A = 0x02 B = A ---------------- REG 0x0002 = A SET_REG1 B = 0x02 DE = DE + 1 ---------------- REG 0x0022 = DE ADD2 0x0023 = 0x0022 + 0x0001 SET_REG2 DE = 0x0023 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0023 = E SUB1 0x41 = 0x64 - 0x23 SET_REG1 A = 0x41 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0023 = E TEST_BIT 0 = bool(0x0023 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0023 = E TEST_BIT 0 = bool(0x0023 & 0x0080) REG 0x0064 = temp0 REG 0x0023 = E SUB1 0x41 = 0x64 - 0x23 TEST_BIT 0 = bool(0x0041 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0023 = E SUB1 0x41 = 0x64 - 0x23 TEST_BIT 0 = bool(0x0041 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0053 = C SET_REG1 A = 0x53 temp2.b = A ---------------- REG 0x0053 = A SET_REG1 temp2 = 0x53 A = A + E ---------------- REG 0x0053 = A REG 0x0023 = E ADD1 0x76 = 0x53 + 0x23 SET_REG1 A = 0x76 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0053 = temp2 REG 0x0023 = E SUB1 0xDC = 0xFF - 0x23 CMP_UGT 0 = 0x0053 > 0x00DC SET_FLAG c = 0 C = A ---------------- REG 0x0076 = A SET_REG1 C = 0x76 A = B ---------------- REG 0x0002 = B SET_REG1 A = 0x02 A = adc.b(A, D, flag:c) ---------------- REG 0x0002 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0002 = 0x0002 + 0x0000 + 0 SET_REG1 A = 0x02 B = A ---------------- REG 0x0002 = A SET_REG1 B = 0x02 DE = DE + 1 ---------------- REG 0x0023 = DE ADD2 0x0024 = 0x0023 + 0x0001 SET_REG2 DE = 0x0024 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0024 = E SUB1 0x40 = 0x64 - 0x24 SET_REG1 A = 0x40 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0024 = E TEST_BIT 0 = bool(0x0024 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0024 = E TEST_BIT 0 = bool(0x0024 & 0x0080) REG 0x0064 = temp0 REG 0x0024 = E SUB1 0x40 = 0x64 - 0x24 TEST_BIT 0 = bool(0x0040 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0024 = E SUB1 0x40 = 0x64 - 0x24 TEST_BIT 0 = bool(0x0040 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0076 = C SET_REG1 A = 0x76 temp2.b = A ---------------- REG 0x0076 = A SET_REG1 temp2 = 0x76 A = A + E ---------------- REG 0x0076 = A REG 0x0024 = E ADD1 0x9A = 0x76 + 0x24 SET_REG1 A = 0x9A flag:c = temp2.b u> 0xff - E ---------------- REG 0x0076 = temp2 REG 0x0024 = E SUB1 0xDB = 0xFF - 0x24 CMP_UGT 0 = 0x0076 > 0x00DB SET_FLAG c = 0 C = A ---------------- REG 0x009A = A SET_REG1 C = 0x9A A = B ---------------- REG 0x0002 = B SET_REG1 A = 0x02 A = adc.b(A, D, flag:c) ---------------- REG 0x0002 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0002 = 0x0002 + 0x0000 + 0 SET_REG1 A = 0x02 B = A ---------------- REG 0x0002 = A SET_REG1 B = 0x02 DE = DE + 1 ---------------- REG 0x0024 = DE ADD2 0x0025 = 0x0024 + 0x0001 SET_REG2 DE = 0x0025 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0025 = E SUB1 0x3F = 0x64 - 0x25 SET_REG1 A = 0x3F flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0025 = E TEST_BIT 0 = bool(0x0025 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0025 = E TEST_BIT 0 = bool(0x0025 & 0x0080) REG 0x0064 = temp0 REG 0x0025 = E SUB1 0x3F = 0x64 - 0x25 TEST_BIT 0 = bool(0x003F & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0025 = E SUB1 0x3F = 0x64 - 0x25 TEST_BIT 0 = bool(0x003F & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x009A = C SET_REG1 A = 0x9A temp2.b = A ---------------- REG 0x009A = A SET_REG1 temp2 = 0x9A A = A + E ---------------- REG 0x009A = A REG 0x0025 = E ADD1 0xBF = 0x9A + 0x25 SET_REG1 A = 0xBF flag:c = temp2.b u> 0xff - E ---------------- REG 0x009A = temp2 REG 0x0025 = E SUB1 0xDA = 0xFF - 0x25 CMP_UGT 0 = 0x009A > 0x00DA SET_FLAG c = 0 C = A ---------------- REG 0x00BF = A SET_REG1 C = 0xBF A = B ---------------- REG 0x0002 = B SET_REG1 A = 0x02 A = adc.b(A, D, flag:c) ---------------- REG 0x0002 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0002 = 0x0002 + 0x0000 + 0 SET_REG1 A = 0x02 B = A ---------------- REG 0x0002 = A SET_REG1 B = 0x02 DE = DE + 1 ---------------- REG 0x0025 = DE ADD2 0x0026 = 0x0025 + 0x0001 SET_REG2 DE = 0x0026 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0026 = E SUB1 0x3E = 0x64 - 0x26 SET_REG1 A = 0x3E flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0026 = E TEST_BIT 0 = bool(0x0026 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0026 = E TEST_BIT 0 = bool(0x0026 & 0x0080) REG 0x0064 = temp0 REG 0x0026 = E SUB1 0x3E = 0x64 - 0x26 TEST_BIT 0 = bool(0x003E & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0026 = E SUB1 0x3E = 0x64 - 0x26 TEST_BIT 0 = bool(0x003E & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00BF = C SET_REG1 A = 0xBF temp2.b = A ---------------- REG 0x00BF = A SET_REG1 temp2 = 0xBF A = A + E ---------------- REG 0x00BF = A REG 0x0026 = E ADD1 0xE5 = 0xBF + 0x26 SET_REG1 A = 0xE5 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00BF = temp2 REG 0x0026 = E SUB1 0xD9 = 0xFF - 0x26 CMP_UGT 0 = 0x00BF > 0x00D9 SET_FLAG c = 0 C = A ---------------- REG 0x00E5 = A SET_REG1 C = 0xE5 A = B ---------------- REG 0x0002 = B SET_REG1 A = 0x02 A = adc.b(A, D, flag:c) ---------------- REG 0x0002 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0002 = 0x0002 + 0x0000 + 0 SET_REG1 A = 0x02 B = A ---------------- REG 0x0002 = A SET_REG1 B = 0x02 DE = DE + 1 ---------------- REG 0x0026 = DE ADD2 0x0027 = 0x0026 + 0x0001 SET_REG2 DE = 0x0027 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0027 = E SUB1 0x3D = 0x64 - 0x27 SET_REG1 A = 0x3D flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0027 = E TEST_BIT 0 = bool(0x0027 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0027 = E TEST_BIT 0 = bool(0x0027 & 0x0080) REG 0x0064 = temp0 REG 0x0027 = E SUB1 0x3D = 0x64 - 0x27 TEST_BIT 0 = bool(0x003D & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0027 = E SUB1 0x3D = 0x64 - 0x27 TEST_BIT 0 = bool(0x003D & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00E5 = C SET_REG1 A = 0xE5 temp2.b = A ---------------- REG 0x00E5 = A SET_REG1 temp2 = 0xE5 A = A + E ---------------- REG 0x00E5 = A REG 0x0027 = E ADD1 0x0C = 0xE5 + 0x27 SET_REG1 A = 0x0C flag:c = temp2.b u> 0xff - E ---------------- REG 0x00E5 = temp2 REG 0x0027 = E SUB1 0xD8 = 0xFF - 0x27 CMP_UGT 1 = 0x00E5 > 0x00D8 SET_FLAG c = 1 C = A ---------------- REG 0x000C = A SET_REG1 C = 0x0C A = B ---------------- REG 0x0002 = B SET_REG1 A = 0x02 A = adc.b(A, D, flag:c) ---------------- REG 0x0002 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0003 = 0x0002 + 0x0000 + 1 SET_REG1 A = 0x03 B = A ---------------- REG 0x0003 = A SET_REG1 B = 0x03 DE = DE + 1 ---------------- REG 0x0027 = DE ADD2 0x0028 = 0x0027 + 0x0001 SET_REG2 DE = 0x0028 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0028 = E SUB1 0x3C = 0x64 - 0x28 SET_REG1 A = 0x3C flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0028 = E TEST_BIT 0 = bool(0x0028 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0028 = E TEST_BIT 0 = bool(0x0028 & 0x0080) REG 0x0064 = temp0 REG 0x0028 = E SUB1 0x3C = 0x64 - 0x28 TEST_BIT 0 = bool(0x003C & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0028 = E SUB1 0x3C = 0x64 - 0x28 TEST_BIT 0 = bool(0x003C & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x000C = C SET_REG1 A = 0x0C temp2.b = A ---------------- REG 0x000C = A SET_REG1 temp2 = 0x0C A = A + E ---------------- REG 0x000C = A REG 0x0028 = E ADD1 0x34 = 0x0C + 0x28 SET_REG1 A = 0x34 flag:c = temp2.b u> 0xff - E ---------------- REG 0x000C = temp2 REG 0x0028 = E SUB1 0xD7 = 0xFF - 0x28 CMP_UGT 0 = 0x000C > 0x00D7 SET_FLAG c = 0 C = A ---------------- REG 0x0034 = A SET_REG1 C = 0x34 A = B ---------------- REG 0x0003 = B SET_REG1 A = 0x03 A = adc.b(A, D, flag:c) ---------------- REG 0x0003 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0003 = 0x0003 + 0x0000 + 0 SET_REG1 A = 0x03 B = A ---------------- REG 0x0003 = A SET_REG1 B = 0x03 DE = DE + 1 ---------------- REG 0x0028 = DE ADD2 0x0029 = 0x0028 + 0x0001 SET_REG2 DE = 0x0029 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0029 = E SUB1 0x3B = 0x64 - 0x29 SET_REG1 A = 0x3B flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0029 = E TEST_BIT 0 = bool(0x0029 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0029 = E TEST_BIT 0 = bool(0x0029 & 0x0080) REG 0x0064 = temp0 REG 0x0029 = E SUB1 0x3B = 0x64 - 0x29 TEST_BIT 0 = bool(0x003B & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0029 = E SUB1 0x3B = 0x64 - 0x29 TEST_BIT 0 = bool(0x003B & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0034 = C SET_REG1 A = 0x34 temp2.b = A ---------------- REG 0x0034 = A SET_REG1 temp2 = 0x34 A = A + E ---------------- REG 0x0034 = A REG 0x0029 = E ADD1 0x5D = 0x34 + 0x29 SET_REG1 A = 0x5D flag:c = temp2.b u> 0xff - E ---------------- REG 0x0034 = temp2 REG 0x0029 = E SUB1 0xD6 = 0xFF - 0x29 CMP_UGT 0 = 0x0034 > 0x00D6 SET_FLAG c = 0 C = A ---------------- REG 0x005D = A SET_REG1 C = 0x5D A = B ---------------- REG 0x0003 = B SET_REG1 A = 0x03 A = adc.b(A, D, flag:c) ---------------- REG 0x0003 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0003 = 0x0003 + 0x0000 + 0 SET_REG1 A = 0x03 B = A ---------------- REG 0x0003 = A SET_REG1 B = 0x03 DE = DE + 1 ---------------- REG 0x0029 = DE ADD2 0x002A = 0x0029 + 0x0001 SET_REG2 DE = 0x002A goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x002A = E SUB1 0x3A = 0x64 - 0x2A SET_REG1 A = 0x3A flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002A = E TEST_BIT 0 = bool(0x002A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002A = E TEST_BIT 0 = bool(0x002A & 0x0080) REG 0x0064 = temp0 REG 0x002A = E SUB1 0x3A = 0x64 - 0x2A TEST_BIT 0 = bool(0x003A & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x002A = E SUB1 0x3A = 0x64 - 0x2A TEST_BIT 0 = bool(0x003A & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x005D = C SET_REG1 A = 0x5D temp2.b = A ---------------- REG 0x005D = A SET_REG1 temp2 = 0x5D A = A + E ---------------- REG 0x005D = A REG 0x002A = E ADD1 0x87 = 0x5D + 0x2A SET_REG1 A = 0x87 flag:c = temp2.b u> 0xff - E ---------------- REG 0x005D = temp2 REG 0x002A = E SUB1 0xD5 = 0xFF - 0x2A CMP_UGT 0 = 0x005D > 0x00D5 SET_FLAG c = 0 C = A ---------------- REG 0x0087 = A SET_REG1 C = 0x87 A = B ---------------- REG 0x0003 = B SET_REG1 A = 0x03 A = adc.b(A, D, flag:c) ---------------- REG 0x0003 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0003 = 0x0003 + 0x0000 + 0 SET_REG1 A = 0x03 B = A ---------------- REG 0x0003 = A SET_REG1 B = 0x03 DE = DE + 1 ---------------- REG 0x002A = DE ADD2 0x002B = 0x002A + 0x0001 SET_REG2 DE = 0x002B goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x002B = E SUB1 0x39 = 0x64 - 0x2B SET_REG1 A = 0x39 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002B = E TEST_BIT 0 = bool(0x002B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002B = E TEST_BIT 0 = bool(0x002B & 0x0080) REG 0x0064 = temp0 REG 0x002B = E SUB1 0x39 = 0x64 - 0x2B TEST_BIT 0 = bool(0x0039 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x002B = E SUB1 0x39 = 0x64 - 0x2B TEST_BIT 0 = bool(0x0039 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0087 = C SET_REG1 A = 0x87 temp2.b = A ---------------- REG 0x0087 = A SET_REG1 temp2 = 0x87 A = A + E ---------------- REG 0x0087 = A REG 0x002B = E ADD1 0xB2 = 0x87 + 0x2B SET_REG1 A = 0xB2 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0087 = temp2 REG 0x002B = E SUB1 0xD4 = 0xFF - 0x2B CMP_UGT 0 = 0x0087 > 0x00D4 SET_FLAG c = 0 C = A ---------------- REG 0x00B2 = A SET_REG1 C = 0xB2 A = B ---------------- REG 0x0003 = B SET_REG1 A = 0x03 A = adc.b(A, D, flag:c) ---------------- REG 0x0003 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0003 = 0x0003 + 0x0000 + 0 SET_REG1 A = 0x03 B = A ---------------- REG 0x0003 = A SET_REG1 B = 0x03 DE = DE + 1 ---------------- REG 0x002B = DE ADD2 0x002C = 0x002B + 0x0001 SET_REG2 DE = 0x002C goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x002C = E SUB1 0x38 = 0x64 - 0x2C SET_REG1 A = 0x38 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002C = E TEST_BIT 0 = bool(0x002C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002C = E TEST_BIT 0 = bool(0x002C & 0x0080) REG 0x0064 = temp0 REG 0x002C = E SUB1 0x38 = 0x64 - 0x2C TEST_BIT 0 = bool(0x0038 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x002C = E SUB1 0x38 = 0x64 - 0x2C TEST_BIT 0 = bool(0x0038 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00B2 = C SET_REG1 A = 0xB2 temp2.b = A ---------------- REG 0x00B2 = A SET_REG1 temp2 = 0xB2 A = A + E ---------------- REG 0x00B2 = A REG 0x002C = E ADD1 0xDE = 0xB2 + 0x2C SET_REG1 A = 0xDE flag:c = temp2.b u> 0xff - E ---------------- REG 0x00B2 = temp2 REG 0x002C = E SUB1 0xD3 = 0xFF - 0x2C CMP_UGT 0 = 0x00B2 > 0x00D3 SET_FLAG c = 0 C = A ---------------- REG 0x00DE = A SET_REG1 C = 0xDE A = B ---------------- REG 0x0003 = B SET_REG1 A = 0x03 A = adc.b(A, D, flag:c) ---------------- REG 0x0003 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0003 = 0x0003 + 0x0000 + 0 SET_REG1 A = 0x03 B = A ---------------- REG 0x0003 = A SET_REG1 B = 0x03 DE = DE + 1 ---------------- REG 0x002C = DE ADD2 0x002D = 0x002C + 0x0001 SET_REG2 DE = 0x002D goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x002D = E SUB1 0x37 = 0x64 - 0x2D SET_REG1 A = 0x37 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002D = E TEST_BIT 0 = bool(0x002D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002D = E TEST_BIT 0 = bool(0x002D & 0x0080) REG 0x0064 = temp0 REG 0x002D = E SUB1 0x37 = 0x64 - 0x2D TEST_BIT 0 = bool(0x0037 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x002D = E SUB1 0x37 = 0x64 - 0x2D TEST_BIT 0 = bool(0x0037 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00DE = C SET_REG1 A = 0xDE temp2.b = A ---------------- REG 0x00DE = A SET_REG1 temp2 = 0xDE A = A + E ---------------- REG 0x00DE = A REG 0x002D = E ADD1 0x0B = 0xDE + 0x2D SET_REG1 A = 0x0B flag:c = temp2.b u> 0xff - E ---------------- REG 0x00DE = temp2 REG 0x002D = E SUB1 0xD2 = 0xFF - 0x2D CMP_UGT 1 = 0x00DE > 0x00D2 SET_FLAG c = 1 C = A ---------------- REG 0x000B = A SET_REG1 C = 0x0B A = B ---------------- REG 0x0003 = B SET_REG1 A = 0x03 A = adc.b(A, D, flag:c) ---------------- REG 0x0003 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0004 = 0x0003 + 0x0000 + 1 SET_REG1 A = 0x04 B = A ---------------- REG 0x0004 = A SET_REG1 B = 0x04 DE = DE + 1 ---------------- REG 0x002D = DE ADD2 0x002E = 0x002D + 0x0001 SET_REG2 DE = 0x002E goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x002E = E SUB1 0x36 = 0x64 - 0x2E SET_REG1 A = 0x36 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002E = E TEST_BIT 0 = bool(0x002E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002E = E TEST_BIT 0 = bool(0x002E & 0x0080) REG 0x0064 = temp0 REG 0x002E = E SUB1 0x36 = 0x64 - 0x2E TEST_BIT 0 = bool(0x0036 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x002E = E SUB1 0x36 = 0x64 - 0x2E TEST_BIT 0 = bool(0x0036 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x000B = C SET_REG1 A = 0x0B temp2.b = A ---------------- REG 0x000B = A SET_REG1 temp2 = 0x0B A = A + E ---------------- REG 0x000B = A REG 0x002E = E ADD1 0x39 = 0x0B + 0x2E SET_REG1 A = 0x39 flag:c = temp2.b u> 0xff - E ---------------- REG 0x000B = temp2 REG 0x002E = E SUB1 0xD1 = 0xFF - 0x2E CMP_UGT 0 = 0x000B > 0x00D1 SET_FLAG c = 0 C = A ---------------- REG 0x0039 = A SET_REG1 C = 0x39 A = B ---------------- REG 0x0004 = B SET_REG1 A = 0x04 A = adc.b(A, D, flag:c) ---------------- REG 0x0004 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0004 = 0x0004 + 0x0000 + 0 SET_REG1 A = 0x04 B = A ---------------- REG 0x0004 = A SET_REG1 B = 0x04 DE = DE + 1 ---------------- REG 0x002E = DE ADD2 0x002F = 0x002E + 0x0001 SET_REG2 DE = 0x002F goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x002F = E SUB1 0x35 = 0x64 - 0x2F SET_REG1 A = 0x35 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002F = E TEST_BIT 0 = bool(0x002F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002F = E TEST_BIT 0 = bool(0x002F & 0x0080) REG 0x0064 = temp0 REG 0x002F = E SUB1 0x35 = 0x64 - 0x2F TEST_BIT 0 = bool(0x0035 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x002F = E SUB1 0x35 = 0x64 - 0x2F TEST_BIT 0 = bool(0x0035 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0039 = C SET_REG1 A = 0x39 temp2.b = A ---------------- REG 0x0039 = A SET_REG1 temp2 = 0x39 A = A + E ---------------- REG 0x0039 = A REG 0x002F = E ADD1 0x68 = 0x39 + 0x2F SET_REG1 A = 0x68 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0039 = temp2 REG 0x002F = E SUB1 0xD0 = 0xFF - 0x2F CMP_UGT 0 = 0x0039 > 0x00D0 SET_FLAG c = 0 C = A ---------------- REG 0x0068 = A SET_REG1 C = 0x68 A = B ---------------- REG 0x0004 = B SET_REG1 A = 0x04 A = adc.b(A, D, flag:c) ---------------- REG 0x0004 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0004 = 0x0004 + 0x0000 + 0 SET_REG1 A = 0x04 B = A ---------------- REG 0x0004 = A SET_REG1 B = 0x04 DE = DE + 1 ---------------- REG 0x002F = DE ADD2 0x0030 = 0x002F + 0x0001 SET_REG2 DE = 0x0030 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0030 = E SUB1 0x34 = 0x64 - 0x30 SET_REG1 A = 0x34 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0030 = E TEST_BIT 0 = bool(0x0030 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0030 = E TEST_BIT 0 = bool(0x0030 & 0x0080) REG 0x0064 = temp0 REG 0x0030 = E SUB1 0x34 = 0x64 - 0x30 TEST_BIT 0 = bool(0x0034 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0030 = E SUB1 0x34 = 0x64 - 0x30 TEST_BIT 0 = bool(0x0034 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0068 = C SET_REG1 A = 0x68 temp2.b = A ---------------- REG 0x0068 = A SET_REG1 temp2 = 0x68 A = A + E ---------------- REG 0x0068 = A REG 0x0030 = E ADD1 0x98 = 0x68 + 0x30 SET_REG1 A = 0x98 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0068 = temp2 REG 0x0030 = E SUB1 0xCF = 0xFF - 0x30 CMP_UGT 0 = 0x0068 > 0x00CF SET_FLAG c = 0 C = A ---------------- REG 0x0098 = A SET_REG1 C = 0x98 A = B ---------------- REG 0x0004 = B SET_REG1 A = 0x04 A = adc.b(A, D, flag:c) ---------------- REG 0x0004 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0004 = 0x0004 + 0x0000 + 0 SET_REG1 A = 0x04 B = A ---------------- REG 0x0004 = A SET_REG1 B = 0x04 DE = DE + 1 ---------------- REG 0x0030 = DE ADD2 0x0031 = 0x0030 + 0x0001 SET_REG2 DE = 0x0031 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0031 = E SUB1 0x33 = 0x64 - 0x31 SET_REG1 A = 0x33 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0031 = E TEST_BIT 0 = bool(0x0031 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0031 = E TEST_BIT 0 = bool(0x0031 & 0x0080) REG 0x0064 = temp0 REG 0x0031 = E SUB1 0x33 = 0x64 - 0x31 TEST_BIT 0 = bool(0x0033 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0031 = E SUB1 0x33 = 0x64 - 0x31 TEST_BIT 0 = bool(0x0033 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0098 = C SET_REG1 A = 0x98 temp2.b = A ---------------- REG 0x0098 = A SET_REG1 temp2 = 0x98 A = A + E ---------------- REG 0x0098 = A REG 0x0031 = E ADD1 0xC9 = 0x98 + 0x31 SET_REG1 A = 0xC9 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0098 = temp2 REG 0x0031 = E SUB1 0xCE = 0xFF - 0x31 CMP_UGT 0 = 0x0098 > 0x00CE SET_FLAG c = 0 C = A ---------------- REG 0x00C9 = A SET_REG1 C = 0xC9 A = B ---------------- REG 0x0004 = B SET_REG1 A = 0x04 A = adc.b(A, D, flag:c) ---------------- REG 0x0004 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0004 = 0x0004 + 0x0000 + 0 SET_REG1 A = 0x04 B = A ---------------- REG 0x0004 = A SET_REG1 B = 0x04 DE = DE + 1 ---------------- REG 0x0031 = DE ADD2 0x0032 = 0x0031 + 0x0001 SET_REG2 DE = 0x0032 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0032 = E SUB1 0x32 = 0x64 - 0x32 SET_REG1 A = 0x32 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0032 = E TEST_BIT 0 = bool(0x0032 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0032 = E TEST_BIT 0 = bool(0x0032 & 0x0080) REG 0x0064 = temp0 REG 0x0032 = E SUB1 0x32 = 0x64 - 0x32 TEST_BIT 0 = bool(0x0032 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0032 = E SUB1 0x32 = 0x64 - 0x32 TEST_BIT 0 = bool(0x0032 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00C9 = C SET_REG1 A = 0xC9 temp2.b = A ---------------- REG 0x00C9 = A SET_REG1 temp2 = 0xC9 A = A + E ---------------- REG 0x00C9 = A REG 0x0032 = E ADD1 0xFB = 0xC9 + 0x32 SET_REG1 A = 0xFB flag:c = temp2.b u> 0xff - E ---------------- REG 0x00C9 = temp2 REG 0x0032 = E SUB1 0xCD = 0xFF - 0x32 CMP_UGT 0 = 0x00C9 > 0x00CD SET_FLAG c = 0 C = A ---------------- REG 0x00FB = A SET_REG1 C = 0xFB A = B ---------------- REG 0x0004 = B SET_REG1 A = 0x04 A = adc.b(A, D, flag:c) ---------------- REG 0x0004 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0004 = 0x0004 + 0x0000 + 0 SET_REG1 A = 0x04 B = A ---------------- REG 0x0004 = A SET_REG1 B = 0x04 DE = DE + 1 ---------------- REG 0x0032 = DE ADD2 0x0033 = 0x0032 + 0x0001 SET_REG2 DE = 0x0033 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0033 = E SUB1 0x31 = 0x64 - 0x33 SET_REG1 A = 0x31 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0033 = E TEST_BIT 0 = bool(0x0033 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0033 = E TEST_BIT 0 = bool(0x0033 & 0x0080) REG 0x0064 = temp0 REG 0x0033 = E SUB1 0x31 = 0x64 - 0x33 TEST_BIT 0 = bool(0x0031 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0033 = E SUB1 0x31 = 0x64 - 0x33 TEST_BIT 0 = bool(0x0031 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00FB = C SET_REG1 A = 0xFB temp2.b = A ---------------- REG 0x00FB = A SET_REG1 temp2 = 0xFB A = A + E ---------------- REG 0x00FB = A REG 0x0033 = E ADD1 0x2E = 0xFB + 0x33 SET_REG1 A = 0x2E flag:c = temp2.b u> 0xff - E ---------------- REG 0x00FB = temp2 REG 0x0033 = E SUB1 0xCC = 0xFF - 0x33 CMP_UGT 1 = 0x00FB > 0x00CC SET_FLAG c = 1 C = A ---------------- REG 0x002E = A SET_REG1 C = 0x2E A = B ---------------- REG 0x0004 = B SET_REG1 A = 0x04 A = adc.b(A, D, flag:c) ---------------- REG 0x0004 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0005 = 0x0004 + 0x0000 + 1 SET_REG1 A = 0x05 B = A ---------------- REG 0x0005 = A SET_REG1 B = 0x05 DE = DE + 1 ---------------- REG 0x0033 = DE ADD2 0x0034 = 0x0033 + 0x0001 SET_REG2 DE = 0x0034 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0034 = E SUB1 0x30 = 0x64 - 0x34 SET_REG1 A = 0x30 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0034 = E TEST_BIT 0 = bool(0x0034 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0034 = E TEST_BIT 0 = bool(0x0034 & 0x0080) REG 0x0064 = temp0 REG 0x0034 = E SUB1 0x30 = 0x64 - 0x34 TEST_BIT 0 = bool(0x0030 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0034 = E SUB1 0x30 = 0x64 - 0x34 TEST_BIT 0 = bool(0x0030 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x002E = C SET_REG1 A = 0x2E temp2.b = A ---------------- REG 0x002E = A SET_REG1 temp2 = 0x2E A = A + E ---------------- REG 0x002E = A REG 0x0034 = E ADD1 0x62 = 0x2E + 0x34 SET_REG1 A = 0x62 flag:c = temp2.b u> 0xff - E ---------------- REG 0x002E = temp2 REG 0x0034 = E SUB1 0xCB = 0xFF - 0x34 CMP_UGT 0 = 0x002E > 0x00CB SET_FLAG c = 0 C = A ---------------- REG 0x0062 = A SET_REG1 C = 0x62 A = B ---------------- REG 0x0005 = B SET_REG1 A = 0x05 A = adc.b(A, D, flag:c) ---------------- REG 0x0005 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0005 = 0x0005 + 0x0000 + 0 SET_REG1 A = 0x05 B = A ---------------- REG 0x0005 = A SET_REG1 B = 0x05 DE = DE + 1 ---------------- REG 0x0034 = DE ADD2 0x0035 = 0x0034 + 0x0001 SET_REG2 DE = 0x0035 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0035 = E SUB1 0x2F = 0x64 - 0x35 SET_REG1 A = 0x2F flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0035 = E TEST_BIT 0 = bool(0x0035 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0035 = E TEST_BIT 0 = bool(0x0035 & 0x0080) REG 0x0064 = temp0 REG 0x0035 = E SUB1 0x2F = 0x64 - 0x35 TEST_BIT 0 = bool(0x002F & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0035 = E SUB1 0x2F = 0x64 - 0x35 TEST_BIT 0 = bool(0x002F & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0062 = C SET_REG1 A = 0x62 temp2.b = A ---------------- REG 0x0062 = A SET_REG1 temp2 = 0x62 A = A + E ---------------- REG 0x0062 = A REG 0x0035 = E ADD1 0x97 = 0x62 + 0x35 SET_REG1 A = 0x97 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0062 = temp2 REG 0x0035 = E SUB1 0xCA = 0xFF - 0x35 CMP_UGT 0 = 0x0062 > 0x00CA SET_FLAG c = 0 C = A ---------------- REG 0x0097 = A SET_REG1 C = 0x97 A = B ---------------- REG 0x0005 = B SET_REG1 A = 0x05 A = adc.b(A, D, flag:c) ---------------- REG 0x0005 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0005 = 0x0005 + 0x0000 + 0 SET_REG1 A = 0x05 B = A ---------------- REG 0x0005 = A SET_REG1 B = 0x05 DE = DE + 1 ---------------- REG 0x0035 = DE ADD2 0x0036 = 0x0035 + 0x0001 SET_REG2 DE = 0x0036 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0036 = E SUB1 0x2E = 0x64 - 0x36 SET_REG1 A = 0x2E flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0036 = E TEST_BIT 0 = bool(0x0036 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0036 = E TEST_BIT 0 = bool(0x0036 & 0x0080) REG 0x0064 = temp0 REG 0x0036 = E SUB1 0x2E = 0x64 - 0x36 TEST_BIT 0 = bool(0x002E & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0036 = E SUB1 0x2E = 0x64 - 0x36 TEST_BIT 0 = bool(0x002E & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0097 = C SET_REG1 A = 0x97 temp2.b = A ---------------- REG 0x0097 = A SET_REG1 temp2 = 0x97 A = A + E ---------------- REG 0x0097 = A REG 0x0036 = E ADD1 0xCD = 0x97 + 0x36 SET_REG1 A = 0xCD flag:c = temp2.b u> 0xff - E ---------------- REG 0x0097 = temp2 REG 0x0036 = E SUB1 0xC9 = 0xFF - 0x36 CMP_UGT 0 = 0x0097 > 0x00C9 SET_FLAG c = 0 C = A ---------------- REG 0x00CD = A SET_REG1 C = 0xCD A = B ---------------- REG 0x0005 = B SET_REG1 A = 0x05 A = adc.b(A, D, flag:c) ---------------- REG 0x0005 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0005 = 0x0005 + 0x0000 + 0 SET_REG1 A = 0x05 B = A ---------------- REG 0x0005 = A SET_REG1 B = 0x05 DE = DE + 1 ---------------- REG 0x0036 = DE ADD2 0x0037 = 0x0036 + 0x0001 SET_REG2 DE = 0x0037 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0037 = E SUB1 0x2D = 0x64 - 0x37 SET_REG1 A = 0x2D flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0037 = E TEST_BIT 0 = bool(0x0037 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0037 = E TEST_BIT 0 = bool(0x0037 & 0x0080) REG 0x0064 = temp0 REG 0x0037 = E SUB1 0x2D = 0x64 - 0x37 TEST_BIT 0 = bool(0x002D & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0037 = E SUB1 0x2D = 0x64 - 0x37 TEST_BIT 0 = bool(0x002D & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00CD = C SET_REG1 A = 0xCD temp2.b = A ---------------- REG 0x00CD = A SET_REG1 temp2 = 0xCD A = A + E ---------------- REG 0x00CD = A REG 0x0037 = E ADD1 0x04 = 0xCD + 0x37 SET_REG1 A = 0x04 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00CD = temp2 REG 0x0037 = E SUB1 0xC8 = 0xFF - 0x37 CMP_UGT 1 = 0x00CD > 0x00C8 SET_FLAG c = 1 C = A ---------------- REG 0x0004 = A SET_REG1 C = 0x04 A = B ---------------- REG 0x0005 = B SET_REG1 A = 0x05 A = adc.b(A, D, flag:c) ---------------- REG 0x0005 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0006 = 0x0005 + 0x0000 + 1 SET_REG1 A = 0x06 B = A ---------------- REG 0x0006 = A SET_REG1 B = 0x06 DE = DE + 1 ---------------- REG 0x0037 = DE ADD2 0x0038 = 0x0037 + 0x0001 SET_REG2 DE = 0x0038 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0038 = E SUB1 0x2C = 0x64 - 0x38 SET_REG1 A = 0x2C flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0038 = E TEST_BIT 0 = bool(0x0038 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0038 = E TEST_BIT 0 = bool(0x0038 & 0x0080) REG 0x0064 = temp0 REG 0x0038 = E SUB1 0x2C = 0x64 - 0x38 TEST_BIT 0 = bool(0x002C & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0038 = E SUB1 0x2C = 0x64 - 0x38 TEST_BIT 0 = bool(0x002C & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0004 = C SET_REG1 A = 0x04 temp2.b = A ---------------- REG 0x0004 = A SET_REG1 temp2 = 0x04 A = A + E ---------------- REG 0x0004 = A REG 0x0038 = E ADD1 0x3C = 0x04 + 0x38 SET_REG1 A = 0x3C flag:c = temp2.b u> 0xff - E ---------------- REG 0x0004 = temp2 REG 0x0038 = E SUB1 0xC7 = 0xFF - 0x38 CMP_UGT 0 = 0x0004 > 0x00C7 SET_FLAG c = 0 C = A ---------------- REG 0x003C = A SET_REG1 C = 0x3C A = B ---------------- REG 0x0006 = B SET_REG1 A = 0x06 A = adc.b(A, D, flag:c) ---------------- REG 0x0006 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0006 = 0x0006 + 0x0000 + 0 SET_REG1 A = 0x06 B = A ---------------- REG 0x0006 = A SET_REG1 B = 0x06 DE = DE + 1 ---------------- REG 0x0038 = DE ADD2 0x0039 = 0x0038 + 0x0001 SET_REG2 DE = 0x0039 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0039 = E SUB1 0x2B = 0x64 - 0x39 SET_REG1 A = 0x2B flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0039 = E TEST_BIT 0 = bool(0x0039 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0039 = E TEST_BIT 0 = bool(0x0039 & 0x0080) REG 0x0064 = temp0 REG 0x0039 = E SUB1 0x2B = 0x64 - 0x39 TEST_BIT 0 = bool(0x002B & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0039 = E SUB1 0x2B = 0x64 - 0x39 TEST_BIT 0 = bool(0x002B & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x003C = C SET_REG1 A = 0x3C temp2.b = A ---------------- REG 0x003C = A SET_REG1 temp2 = 0x3C A = A + E ---------------- REG 0x003C = A REG 0x0039 = E ADD1 0x75 = 0x3C + 0x39 SET_REG1 A = 0x75 flag:c = temp2.b u> 0xff - E ---------------- REG 0x003C = temp2 REG 0x0039 = E SUB1 0xC6 = 0xFF - 0x39 CMP_UGT 0 = 0x003C > 0x00C6 SET_FLAG c = 0 C = A ---------------- REG 0x0075 = A SET_REG1 C = 0x75 A = B ---------------- REG 0x0006 = B SET_REG1 A = 0x06 A = adc.b(A, D, flag:c) ---------------- REG 0x0006 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0006 = 0x0006 + 0x0000 + 0 SET_REG1 A = 0x06 B = A ---------------- REG 0x0006 = A SET_REG1 B = 0x06 DE = DE + 1 ---------------- REG 0x0039 = DE ADD2 0x003A = 0x0039 + 0x0001 SET_REG2 DE = 0x003A goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x003A = E SUB1 0x2A = 0x64 - 0x3A SET_REG1 A = 0x2A flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003A = E TEST_BIT 0 = bool(0x003A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003A = E TEST_BIT 0 = bool(0x003A & 0x0080) REG 0x0064 = temp0 REG 0x003A = E SUB1 0x2A = 0x64 - 0x3A TEST_BIT 0 = bool(0x002A & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x003A = E SUB1 0x2A = 0x64 - 0x3A TEST_BIT 0 = bool(0x002A & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0075 = C SET_REG1 A = 0x75 temp2.b = A ---------------- REG 0x0075 = A SET_REG1 temp2 = 0x75 A = A + E ---------------- REG 0x0075 = A REG 0x003A = E ADD1 0xAF = 0x75 + 0x3A SET_REG1 A = 0xAF flag:c = temp2.b u> 0xff - E ---------------- REG 0x0075 = temp2 REG 0x003A = E SUB1 0xC5 = 0xFF - 0x3A CMP_UGT 0 = 0x0075 > 0x00C5 SET_FLAG c = 0 C = A ---------------- REG 0x00AF = A SET_REG1 C = 0xAF A = B ---------------- REG 0x0006 = B SET_REG1 A = 0x06 A = adc.b(A, D, flag:c) ---------------- REG 0x0006 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0006 = 0x0006 + 0x0000 + 0 SET_REG1 A = 0x06 B = A ---------------- REG 0x0006 = A SET_REG1 B = 0x06 DE = DE + 1 ---------------- REG 0x003A = DE ADD2 0x003B = 0x003A + 0x0001 SET_REG2 DE = 0x003B goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x003B = E SUB1 0x29 = 0x64 - 0x3B SET_REG1 A = 0x29 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003B = E TEST_BIT 0 = bool(0x003B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003B = E TEST_BIT 0 = bool(0x003B & 0x0080) REG 0x0064 = temp0 REG 0x003B = E SUB1 0x29 = 0x64 - 0x3B TEST_BIT 0 = bool(0x0029 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x003B = E SUB1 0x29 = 0x64 - 0x3B TEST_BIT 0 = bool(0x0029 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00AF = C SET_REG1 A = 0xAF temp2.b = A ---------------- REG 0x00AF = A SET_REG1 temp2 = 0xAF A = A + E ---------------- REG 0x00AF = A REG 0x003B = E ADD1 0xEA = 0xAF + 0x3B SET_REG1 A = 0xEA flag:c = temp2.b u> 0xff - E ---------------- REG 0x00AF = temp2 REG 0x003B = E SUB1 0xC4 = 0xFF - 0x3B CMP_UGT 0 = 0x00AF > 0x00C4 SET_FLAG c = 0 C = A ---------------- REG 0x00EA = A SET_REG1 C = 0xEA A = B ---------------- REG 0x0006 = B SET_REG1 A = 0x06 A = adc.b(A, D, flag:c) ---------------- REG 0x0006 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0006 = 0x0006 + 0x0000 + 0 SET_REG1 A = 0x06 B = A ---------------- REG 0x0006 = A SET_REG1 B = 0x06 DE = DE + 1 ---------------- REG 0x003B = DE ADD2 0x003C = 0x003B + 0x0001 SET_REG2 DE = 0x003C goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x003C = E SUB1 0x28 = 0x64 - 0x3C SET_REG1 A = 0x28 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003C = E TEST_BIT 0 = bool(0x003C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003C = E TEST_BIT 0 = bool(0x003C & 0x0080) REG 0x0064 = temp0 REG 0x003C = E SUB1 0x28 = 0x64 - 0x3C TEST_BIT 0 = bool(0x0028 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x003C = E SUB1 0x28 = 0x64 - 0x3C TEST_BIT 0 = bool(0x0028 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00EA = C SET_REG1 A = 0xEA temp2.b = A ---------------- REG 0x00EA = A SET_REG1 temp2 = 0xEA A = A + E ---------------- REG 0x00EA = A REG 0x003C = E ADD1 0x26 = 0xEA + 0x3C SET_REG1 A = 0x26 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00EA = temp2 REG 0x003C = E SUB1 0xC3 = 0xFF - 0x3C CMP_UGT 1 = 0x00EA > 0x00C3 SET_FLAG c = 1 C = A ---------------- REG 0x0026 = A SET_REG1 C = 0x26 A = B ---------------- REG 0x0006 = B SET_REG1 A = 0x06 A = adc.b(A, D, flag:c) ---------------- REG 0x0006 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0007 = 0x0006 + 0x0000 + 1 SET_REG1 A = 0x07 B = A ---------------- REG 0x0007 = A SET_REG1 B = 0x07 DE = DE + 1 ---------------- REG 0x003C = DE ADD2 0x003D = 0x003C + 0x0001 SET_REG2 DE = 0x003D goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x003D = E SUB1 0x27 = 0x64 - 0x3D SET_REG1 A = 0x27 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003D = E TEST_BIT 0 = bool(0x003D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003D = E TEST_BIT 0 = bool(0x003D & 0x0080) REG 0x0064 = temp0 REG 0x003D = E SUB1 0x27 = 0x64 - 0x3D TEST_BIT 0 = bool(0x0027 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x003D = E SUB1 0x27 = 0x64 - 0x3D TEST_BIT 0 = bool(0x0027 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0026 = C SET_REG1 A = 0x26 temp2.b = A ---------------- REG 0x0026 = A SET_REG1 temp2 = 0x26 A = A + E ---------------- REG 0x0026 = A REG 0x003D = E ADD1 0x63 = 0x26 + 0x3D SET_REG1 A = 0x63 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0026 = temp2 REG 0x003D = E SUB1 0xC2 = 0xFF - 0x3D CMP_UGT 0 = 0x0026 > 0x00C2 SET_FLAG c = 0 C = A ---------------- REG 0x0063 = A SET_REG1 C = 0x63 A = B ---------------- REG 0x0007 = B SET_REG1 A = 0x07 A = adc.b(A, D, flag:c) ---------------- REG 0x0007 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0007 = 0x0007 + 0x0000 + 0 SET_REG1 A = 0x07 B = A ---------------- REG 0x0007 = A SET_REG1 B = 0x07 DE = DE + 1 ---------------- REG 0x003D = DE ADD2 0x003E = 0x003D + 0x0001 SET_REG2 DE = 0x003E goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x003E = E SUB1 0x26 = 0x64 - 0x3E SET_REG1 A = 0x26 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003E = E TEST_BIT 0 = bool(0x003E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003E = E TEST_BIT 0 = bool(0x003E & 0x0080) REG 0x0064 = temp0 REG 0x003E = E SUB1 0x26 = 0x64 - 0x3E TEST_BIT 0 = bool(0x0026 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x003E = E SUB1 0x26 = 0x64 - 0x3E TEST_BIT 0 = bool(0x0026 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0063 = C SET_REG1 A = 0x63 temp2.b = A ---------------- REG 0x0063 = A SET_REG1 temp2 = 0x63 A = A + E ---------------- REG 0x0063 = A REG 0x003E = E ADD1 0xA1 = 0x63 + 0x3E SET_REG1 A = 0xA1 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0063 = temp2 REG 0x003E = E SUB1 0xC1 = 0xFF - 0x3E CMP_UGT 0 = 0x0063 > 0x00C1 SET_FLAG c = 0 C = A ---------------- REG 0x00A1 = A SET_REG1 C = 0xA1 A = B ---------------- REG 0x0007 = B SET_REG1 A = 0x07 A = adc.b(A, D, flag:c) ---------------- REG 0x0007 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0007 = 0x0007 + 0x0000 + 0 SET_REG1 A = 0x07 B = A ---------------- REG 0x0007 = A SET_REG1 B = 0x07 DE = DE + 1 ---------------- REG 0x003E = DE ADD2 0x003F = 0x003E + 0x0001 SET_REG2 DE = 0x003F goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x003F = E SUB1 0x25 = 0x64 - 0x3F SET_REG1 A = 0x25 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003F = E TEST_BIT 0 = bool(0x003F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003F = E TEST_BIT 0 = bool(0x003F & 0x0080) REG 0x0064 = temp0 REG 0x003F = E SUB1 0x25 = 0x64 - 0x3F TEST_BIT 0 = bool(0x0025 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x003F = E SUB1 0x25 = 0x64 - 0x3F TEST_BIT 0 = bool(0x0025 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00A1 = C SET_REG1 A = 0xA1 temp2.b = A ---------------- REG 0x00A1 = A SET_REG1 temp2 = 0xA1 A = A + E ---------------- REG 0x00A1 = A REG 0x003F = E ADD1 0xE0 = 0xA1 + 0x3F SET_REG1 A = 0xE0 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00A1 = temp2 REG 0x003F = E SUB1 0xC0 = 0xFF - 0x3F CMP_UGT 0 = 0x00A1 > 0x00C0 SET_FLAG c = 0 C = A ---------------- REG 0x00E0 = A SET_REG1 C = 0xE0 A = B ---------------- REG 0x0007 = B SET_REG1 A = 0x07 A = adc.b(A, D, flag:c) ---------------- REG 0x0007 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0007 = 0x0007 + 0x0000 + 0 SET_REG1 A = 0x07 B = A ---------------- REG 0x0007 = A SET_REG1 B = 0x07 DE = DE + 1 ---------------- REG 0x003F = DE ADD2 0x0040 = 0x003F + 0x0001 SET_REG2 DE = 0x0040 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0040 = E SUB1 0x24 = 0x64 - 0x40 SET_REG1 A = 0x24 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0040 = E TEST_BIT 0 = bool(0x0040 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0040 = E TEST_BIT 0 = bool(0x0040 & 0x0080) REG 0x0064 = temp0 REG 0x0040 = E SUB1 0x24 = 0x64 - 0x40 TEST_BIT 0 = bool(0x0024 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0040 = E SUB1 0x24 = 0x64 - 0x40 TEST_BIT 0 = bool(0x0024 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00E0 = C SET_REG1 A = 0xE0 temp2.b = A ---------------- REG 0x00E0 = A SET_REG1 temp2 = 0xE0 A = A + E ---------------- REG 0x00E0 = A REG 0x0040 = E ADD1 0x20 = 0xE0 + 0x40 SET_REG1 A = 0x20 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00E0 = temp2 REG 0x0040 = E SUB1 0xBF = 0xFF - 0x40 CMP_UGT 1 = 0x00E0 > 0x00BF SET_FLAG c = 1 C = A ---------------- REG 0x0020 = A SET_REG1 C = 0x20 A = B ---------------- REG 0x0007 = B SET_REG1 A = 0x07 A = adc.b(A, D, flag:c) ---------------- REG 0x0007 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0008 = 0x0007 + 0x0000 + 1 SET_REG1 A = 0x08 B = A ---------------- REG 0x0008 = A SET_REG1 B = 0x08 DE = DE + 1 ---------------- REG 0x0040 = DE ADD2 0x0041 = 0x0040 + 0x0001 SET_REG2 DE = 0x0041 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0041 = E SUB1 0x23 = 0x64 - 0x41 SET_REG1 A = 0x23 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0041 = E TEST_BIT 0 = bool(0x0041 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0041 = E TEST_BIT 0 = bool(0x0041 & 0x0080) REG 0x0064 = temp0 REG 0x0041 = E SUB1 0x23 = 0x64 - 0x41 TEST_BIT 0 = bool(0x0023 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0041 = E SUB1 0x23 = 0x64 - 0x41 TEST_BIT 0 = bool(0x0023 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0020 = C SET_REG1 A = 0x20 temp2.b = A ---------------- REG 0x0020 = A SET_REG1 temp2 = 0x20 A = A + E ---------------- REG 0x0020 = A REG 0x0041 = E ADD1 0x61 = 0x20 + 0x41 SET_REG1 A = 0x61 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0020 = temp2 REG 0x0041 = E SUB1 0xBE = 0xFF - 0x41 CMP_UGT 0 = 0x0020 > 0x00BE SET_FLAG c = 0 C = A ---------------- REG 0x0061 = A SET_REG1 C = 0x61 A = B ---------------- REG 0x0008 = B SET_REG1 A = 0x08 A = adc.b(A, D, flag:c) ---------------- REG 0x0008 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0008 = 0x0008 + 0x0000 + 0 SET_REG1 A = 0x08 B = A ---------------- REG 0x0008 = A SET_REG1 B = 0x08 DE = DE + 1 ---------------- REG 0x0041 = DE ADD2 0x0042 = 0x0041 + 0x0001 SET_REG2 DE = 0x0042 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0042 = E SUB1 0x22 = 0x64 - 0x42 SET_REG1 A = 0x22 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0042 = E TEST_BIT 0 = bool(0x0042 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0042 = E TEST_BIT 0 = bool(0x0042 & 0x0080) REG 0x0064 = temp0 REG 0x0042 = E SUB1 0x22 = 0x64 - 0x42 TEST_BIT 0 = bool(0x0022 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0042 = E SUB1 0x22 = 0x64 - 0x42 TEST_BIT 0 = bool(0x0022 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0061 = C SET_REG1 A = 0x61 temp2.b = A ---------------- REG 0x0061 = A SET_REG1 temp2 = 0x61 A = A + E ---------------- REG 0x0061 = A REG 0x0042 = E ADD1 0xA3 = 0x61 + 0x42 SET_REG1 A = 0xA3 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0061 = temp2 REG 0x0042 = E SUB1 0xBD = 0xFF - 0x42 CMP_UGT 0 = 0x0061 > 0x00BD SET_FLAG c = 0 C = A ---------------- REG 0x00A3 = A SET_REG1 C = 0xA3 A = B ---------------- REG 0x0008 = B SET_REG1 A = 0x08 A = adc.b(A, D, flag:c) ---------------- REG 0x0008 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0008 = 0x0008 + 0x0000 + 0 SET_REG1 A = 0x08 B = A ---------------- REG 0x0008 = A SET_REG1 B = 0x08 DE = DE + 1 ---------------- REG 0x0042 = DE ADD2 0x0043 = 0x0042 + 0x0001 SET_REG2 DE = 0x0043 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0043 = E SUB1 0x21 = 0x64 - 0x43 SET_REG1 A = 0x21 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0043 = E TEST_BIT 0 = bool(0x0043 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0043 = E TEST_BIT 0 = bool(0x0043 & 0x0080) REG 0x0064 = temp0 REG 0x0043 = E SUB1 0x21 = 0x64 - 0x43 TEST_BIT 0 = bool(0x0021 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0043 = E SUB1 0x21 = 0x64 - 0x43 TEST_BIT 0 = bool(0x0021 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00A3 = C SET_REG1 A = 0xA3 temp2.b = A ---------------- REG 0x00A3 = A SET_REG1 temp2 = 0xA3 A = A + E ---------------- REG 0x00A3 = A REG 0x0043 = E ADD1 0xE6 = 0xA3 + 0x43 SET_REG1 A = 0xE6 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00A3 = temp2 REG 0x0043 = E SUB1 0xBC = 0xFF - 0x43 CMP_UGT 0 = 0x00A3 > 0x00BC SET_FLAG c = 0 C = A ---------------- REG 0x00E6 = A SET_REG1 C = 0xE6 A = B ---------------- REG 0x0008 = B SET_REG1 A = 0x08 A = adc.b(A, D, flag:c) ---------------- REG 0x0008 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0008 = 0x0008 + 0x0000 + 0 SET_REG1 A = 0x08 B = A ---------------- REG 0x0008 = A SET_REG1 B = 0x08 DE = DE + 1 ---------------- REG 0x0043 = DE ADD2 0x0044 = 0x0043 + 0x0001 SET_REG2 DE = 0x0044 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0044 = E SUB1 0x20 = 0x64 - 0x44 SET_REG1 A = 0x20 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0044 = E TEST_BIT 0 = bool(0x0044 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0044 = E TEST_BIT 0 = bool(0x0044 & 0x0080) REG 0x0064 = temp0 REG 0x0044 = E SUB1 0x20 = 0x64 - 0x44 TEST_BIT 0 = bool(0x0020 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0044 = E SUB1 0x20 = 0x64 - 0x44 TEST_BIT 0 = bool(0x0020 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00E6 = C SET_REG1 A = 0xE6 temp2.b = A ---------------- REG 0x00E6 = A SET_REG1 temp2 = 0xE6 A = A + E ---------------- REG 0x00E6 = A REG 0x0044 = E ADD1 0x2A = 0xE6 + 0x44 SET_REG1 A = 0x2A flag:c = temp2.b u> 0xff - E ---------------- REG 0x00E6 = temp2 REG 0x0044 = E SUB1 0xBB = 0xFF - 0x44 CMP_UGT 1 = 0x00E6 > 0x00BB SET_FLAG c = 1 C = A ---------------- REG 0x002A = A SET_REG1 C = 0x2A A = B ---------------- REG 0x0008 = B SET_REG1 A = 0x08 A = adc.b(A, D, flag:c) ---------------- REG 0x0008 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0009 = 0x0008 + 0x0000 + 1 SET_REG1 A = 0x09 B = A ---------------- REG 0x0009 = A SET_REG1 B = 0x09 DE = DE + 1 ---------------- REG 0x0044 = DE ADD2 0x0045 = 0x0044 + 0x0001 SET_REG2 DE = 0x0045 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0045 = E SUB1 0x1F = 0x64 - 0x45 SET_REG1 A = 0x1F flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0045 = E TEST_BIT 0 = bool(0x0045 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0045 = E TEST_BIT 0 = bool(0x0045 & 0x0080) REG 0x0064 = temp0 REG 0x0045 = E SUB1 0x1F = 0x64 - 0x45 TEST_BIT 0 = bool(0x001F & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0045 = E SUB1 0x1F = 0x64 - 0x45 TEST_BIT 0 = bool(0x001F & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x002A = C SET_REG1 A = 0x2A temp2.b = A ---------------- REG 0x002A = A SET_REG1 temp2 = 0x2A A = A + E ---------------- REG 0x002A = A REG 0x0045 = E ADD1 0x6F = 0x2A + 0x45 SET_REG1 A = 0x6F flag:c = temp2.b u> 0xff - E ---------------- REG 0x002A = temp2 REG 0x0045 = E SUB1 0xBA = 0xFF - 0x45 CMP_UGT 0 = 0x002A > 0x00BA SET_FLAG c = 0 C = A ---------------- REG 0x006F = A SET_REG1 C = 0x6F A = B ---------------- REG 0x0009 = B SET_REG1 A = 0x09 A = adc.b(A, D, flag:c) ---------------- REG 0x0009 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0009 = 0x0009 + 0x0000 + 0 SET_REG1 A = 0x09 B = A ---------------- REG 0x0009 = A SET_REG1 B = 0x09 DE = DE + 1 ---------------- REG 0x0045 = DE ADD2 0x0046 = 0x0045 + 0x0001 SET_REG2 DE = 0x0046 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0046 = E SUB1 0x1E = 0x64 - 0x46 SET_REG1 A = 0x1E flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0046 = E TEST_BIT 0 = bool(0x0046 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0046 = E TEST_BIT 0 = bool(0x0046 & 0x0080) REG 0x0064 = temp0 REG 0x0046 = E SUB1 0x1E = 0x64 - 0x46 TEST_BIT 0 = bool(0x001E & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0046 = E SUB1 0x1E = 0x64 - 0x46 TEST_BIT 0 = bool(0x001E & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x006F = C SET_REG1 A = 0x6F temp2.b = A ---------------- REG 0x006F = A SET_REG1 temp2 = 0x6F A = A + E ---------------- REG 0x006F = A REG 0x0046 = E ADD1 0xB5 = 0x6F + 0x46 SET_REG1 A = 0xB5 flag:c = temp2.b u> 0xff - E ---------------- REG 0x006F = temp2 REG 0x0046 = E SUB1 0xB9 = 0xFF - 0x46 CMP_UGT 0 = 0x006F > 0x00B9 SET_FLAG c = 0 C = A ---------------- REG 0x00B5 = A SET_REG1 C = 0xB5 A = B ---------------- REG 0x0009 = B SET_REG1 A = 0x09 A = adc.b(A, D, flag:c) ---------------- REG 0x0009 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0009 = 0x0009 + 0x0000 + 0 SET_REG1 A = 0x09 B = A ---------------- REG 0x0009 = A SET_REG1 B = 0x09 DE = DE + 1 ---------------- REG 0x0046 = DE ADD2 0x0047 = 0x0046 + 0x0001 SET_REG2 DE = 0x0047 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0047 = E SUB1 0x1D = 0x64 - 0x47 SET_REG1 A = 0x1D flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0047 = E TEST_BIT 0 = bool(0x0047 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0047 = E TEST_BIT 0 = bool(0x0047 & 0x0080) REG 0x0064 = temp0 REG 0x0047 = E SUB1 0x1D = 0x64 - 0x47 TEST_BIT 0 = bool(0x001D & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0047 = E SUB1 0x1D = 0x64 - 0x47 TEST_BIT 0 = bool(0x001D & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00B5 = C SET_REG1 A = 0xB5 temp2.b = A ---------------- REG 0x00B5 = A SET_REG1 temp2 = 0xB5 A = A + E ---------------- REG 0x00B5 = A REG 0x0047 = E ADD1 0xFC = 0xB5 + 0x47 SET_REG1 A = 0xFC flag:c = temp2.b u> 0xff - E ---------------- REG 0x00B5 = temp2 REG 0x0047 = E SUB1 0xB8 = 0xFF - 0x47 CMP_UGT 0 = 0x00B5 > 0x00B8 SET_FLAG c = 0 C = A ---------------- REG 0x00FC = A SET_REG1 C = 0xFC A = B ---------------- REG 0x0009 = B SET_REG1 A = 0x09 A = adc.b(A, D, flag:c) ---------------- REG 0x0009 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0009 = 0x0009 + 0x0000 + 0 SET_REG1 A = 0x09 B = A ---------------- REG 0x0009 = A SET_REG1 B = 0x09 DE = DE + 1 ---------------- REG 0x0047 = DE ADD2 0x0048 = 0x0047 + 0x0001 SET_REG2 DE = 0x0048 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0048 = E SUB1 0x1C = 0x64 - 0x48 SET_REG1 A = 0x1C flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0048 = E TEST_BIT 0 = bool(0x0048 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0048 = E TEST_BIT 0 = bool(0x0048 & 0x0080) REG 0x0064 = temp0 REG 0x0048 = E SUB1 0x1C = 0x64 - 0x48 TEST_BIT 0 = bool(0x001C & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0048 = E SUB1 0x1C = 0x64 - 0x48 TEST_BIT 0 = bool(0x001C & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00FC = C SET_REG1 A = 0xFC temp2.b = A ---------------- REG 0x00FC = A SET_REG1 temp2 = 0xFC A = A + E ---------------- REG 0x00FC = A REG 0x0048 = E ADD1 0x44 = 0xFC + 0x48 SET_REG1 A = 0x44 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00FC = temp2 REG 0x0048 = E SUB1 0xB7 = 0xFF - 0x48 CMP_UGT 1 = 0x00FC > 0x00B7 SET_FLAG c = 1 C = A ---------------- REG 0x0044 = A SET_REG1 C = 0x44 A = B ---------------- REG 0x0009 = B SET_REG1 A = 0x09 A = adc.b(A, D, flag:c) ---------------- REG 0x0009 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000A = 0x0009 + 0x0000 + 1 SET_REG1 A = 0x0A B = A ---------------- REG 0x000A = A SET_REG1 B = 0x0A DE = DE + 1 ---------------- REG 0x0048 = DE ADD2 0x0049 = 0x0048 + 0x0001 SET_REG2 DE = 0x0049 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0049 = E SUB1 0x1B = 0x64 - 0x49 SET_REG1 A = 0x1B flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0049 = E TEST_BIT 0 = bool(0x0049 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0049 = E TEST_BIT 0 = bool(0x0049 & 0x0080) REG 0x0064 = temp0 REG 0x0049 = E SUB1 0x1B = 0x64 - 0x49 TEST_BIT 0 = bool(0x001B & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0049 = E SUB1 0x1B = 0x64 - 0x49 TEST_BIT 0 = bool(0x001B & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0044 = C SET_REG1 A = 0x44 temp2.b = A ---------------- REG 0x0044 = A SET_REG1 temp2 = 0x44 A = A + E ---------------- REG 0x0044 = A REG 0x0049 = E ADD1 0x8D = 0x44 + 0x49 SET_REG1 A = 0x8D flag:c = temp2.b u> 0xff - E ---------------- REG 0x0044 = temp2 REG 0x0049 = E SUB1 0xB6 = 0xFF - 0x49 CMP_UGT 0 = 0x0044 > 0x00B6 SET_FLAG c = 0 C = A ---------------- REG 0x008D = A SET_REG1 C = 0x8D A = B ---------------- REG 0x000A = B SET_REG1 A = 0x0A A = adc.b(A, D, flag:c) ---------------- REG 0x000A = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000A = 0x000A + 0x0000 + 0 SET_REG1 A = 0x0A B = A ---------------- REG 0x000A = A SET_REG1 B = 0x0A DE = DE + 1 ---------------- REG 0x0049 = DE ADD2 0x004A = 0x0049 + 0x0001 SET_REG2 DE = 0x004A goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x004A = E SUB1 0x1A = 0x64 - 0x4A SET_REG1 A = 0x1A flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004A = E TEST_BIT 0 = bool(0x004A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004A = E TEST_BIT 0 = bool(0x004A & 0x0080) REG 0x0064 = temp0 REG 0x004A = E SUB1 0x1A = 0x64 - 0x4A TEST_BIT 0 = bool(0x001A & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x004A = E SUB1 0x1A = 0x64 - 0x4A TEST_BIT 0 = bool(0x001A & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x008D = C SET_REG1 A = 0x8D temp2.b = A ---------------- REG 0x008D = A SET_REG1 temp2 = 0x8D A = A + E ---------------- REG 0x008D = A REG 0x004A = E ADD1 0xD7 = 0x8D + 0x4A SET_REG1 A = 0xD7 flag:c = temp2.b u> 0xff - E ---------------- REG 0x008D = temp2 REG 0x004A = E SUB1 0xB5 = 0xFF - 0x4A CMP_UGT 0 = 0x008D > 0x00B5 SET_FLAG c = 0 C = A ---------------- REG 0x00D7 = A SET_REG1 C = 0xD7 A = B ---------------- REG 0x000A = B SET_REG1 A = 0x0A A = adc.b(A, D, flag:c) ---------------- REG 0x000A = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000A = 0x000A + 0x0000 + 0 SET_REG1 A = 0x0A B = A ---------------- REG 0x000A = A SET_REG1 B = 0x0A DE = DE + 1 ---------------- REG 0x004A = DE ADD2 0x004B = 0x004A + 0x0001 SET_REG2 DE = 0x004B goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x004B = E SUB1 0x19 = 0x64 - 0x4B SET_REG1 A = 0x19 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004B = E TEST_BIT 0 = bool(0x004B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004B = E TEST_BIT 0 = bool(0x004B & 0x0080) REG 0x0064 = temp0 REG 0x004B = E SUB1 0x19 = 0x64 - 0x4B TEST_BIT 0 = bool(0x0019 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x004B = E SUB1 0x19 = 0x64 - 0x4B TEST_BIT 0 = bool(0x0019 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00D7 = C SET_REG1 A = 0xD7 temp2.b = A ---------------- REG 0x00D7 = A SET_REG1 temp2 = 0xD7 A = A + E ---------------- REG 0x00D7 = A REG 0x004B = E ADD1 0x22 = 0xD7 + 0x4B SET_REG1 A = 0x22 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00D7 = temp2 REG 0x004B = E SUB1 0xB4 = 0xFF - 0x4B CMP_UGT 1 = 0x00D7 > 0x00B4 SET_FLAG c = 1 C = A ---------------- REG 0x0022 = A SET_REG1 C = 0x22 A = B ---------------- REG 0x000A = B SET_REG1 A = 0x0A A = adc.b(A, D, flag:c) ---------------- REG 0x000A = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000B = 0x000A + 0x0000 + 1 SET_REG1 A = 0x0B B = A ---------------- REG 0x000B = A SET_REG1 B = 0x0B DE = DE + 1 ---------------- REG 0x004B = DE ADD2 0x004C = 0x004B + 0x0001 SET_REG2 DE = 0x004C goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x004C = E SUB1 0x18 = 0x64 - 0x4C SET_REG1 A = 0x18 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004C = E TEST_BIT 0 = bool(0x004C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004C = E TEST_BIT 0 = bool(0x004C & 0x0080) REG 0x0064 = temp0 REG 0x004C = E SUB1 0x18 = 0x64 - 0x4C TEST_BIT 0 = bool(0x0018 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x004C = E SUB1 0x18 = 0x64 - 0x4C TEST_BIT 0 = bool(0x0018 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0022 = C SET_REG1 A = 0x22 temp2.b = A ---------------- REG 0x0022 = A SET_REG1 temp2 = 0x22 A = A + E ---------------- REG 0x0022 = A REG 0x004C = E ADD1 0x6E = 0x22 + 0x4C SET_REG1 A = 0x6E flag:c = temp2.b u> 0xff - E ---------------- REG 0x0022 = temp2 REG 0x004C = E SUB1 0xB3 = 0xFF - 0x4C CMP_UGT 0 = 0x0022 > 0x00B3 SET_FLAG c = 0 C = A ---------------- REG 0x006E = A SET_REG1 C = 0x6E A = B ---------------- REG 0x000B = B SET_REG1 A = 0x0B A = adc.b(A, D, flag:c) ---------------- REG 0x000B = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000B = 0x000B + 0x0000 + 0 SET_REG1 A = 0x0B B = A ---------------- REG 0x000B = A SET_REG1 B = 0x0B DE = DE + 1 ---------------- REG 0x004C = DE ADD2 0x004D = 0x004C + 0x0001 SET_REG2 DE = 0x004D goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x004D = E SUB1 0x17 = 0x64 - 0x4D SET_REG1 A = 0x17 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004D = E TEST_BIT 0 = bool(0x004D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004D = E TEST_BIT 0 = bool(0x004D & 0x0080) REG 0x0064 = temp0 REG 0x004D = E SUB1 0x17 = 0x64 - 0x4D TEST_BIT 0 = bool(0x0017 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x004D = E SUB1 0x17 = 0x64 - 0x4D TEST_BIT 0 = bool(0x0017 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x006E = C SET_REG1 A = 0x6E temp2.b = A ---------------- REG 0x006E = A SET_REG1 temp2 = 0x6E A = A + E ---------------- REG 0x006E = A REG 0x004D = E ADD1 0xBB = 0x6E + 0x4D SET_REG1 A = 0xBB flag:c = temp2.b u> 0xff - E ---------------- REG 0x006E = temp2 REG 0x004D = E SUB1 0xB2 = 0xFF - 0x4D CMP_UGT 0 = 0x006E > 0x00B2 SET_FLAG c = 0 C = A ---------------- REG 0x00BB = A SET_REG1 C = 0xBB A = B ---------------- REG 0x000B = B SET_REG1 A = 0x0B A = adc.b(A, D, flag:c) ---------------- REG 0x000B = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000B = 0x000B + 0x0000 + 0 SET_REG1 A = 0x0B B = A ---------------- REG 0x000B = A SET_REG1 B = 0x0B DE = DE + 1 ---------------- REG 0x004D = DE ADD2 0x004E = 0x004D + 0x0001 SET_REG2 DE = 0x004E goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x004E = E SUB1 0x16 = 0x64 - 0x4E SET_REG1 A = 0x16 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004E = E TEST_BIT 0 = bool(0x004E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004E = E TEST_BIT 0 = bool(0x004E & 0x0080) REG 0x0064 = temp0 REG 0x004E = E SUB1 0x16 = 0x64 - 0x4E TEST_BIT 0 = bool(0x0016 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x004E = E SUB1 0x16 = 0x64 - 0x4E TEST_BIT 0 = bool(0x0016 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00BB = C SET_REG1 A = 0xBB temp2.b = A ---------------- REG 0x00BB = A SET_REG1 temp2 = 0xBB A = A + E ---------------- REG 0x00BB = A REG 0x004E = E ADD1 0x09 = 0xBB + 0x4E SET_REG1 A = 0x09 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00BB = temp2 REG 0x004E = E SUB1 0xB1 = 0xFF - 0x4E CMP_UGT 1 = 0x00BB > 0x00B1 SET_FLAG c = 1 C = A ---------------- REG 0x0009 = A SET_REG1 C = 0x09 A = B ---------------- REG 0x000B = B SET_REG1 A = 0x0B A = adc.b(A, D, flag:c) ---------------- REG 0x000B = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000C = 0x000B + 0x0000 + 1 SET_REG1 A = 0x0C B = A ---------------- REG 0x000C = A SET_REG1 B = 0x0C DE = DE + 1 ---------------- REG 0x004E = DE ADD2 0x004F = 0x004E + 0x0001 SET_REG2 DE = 0x004F goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x004F = E SUB1 0x15 = 0x64 - 0x4F SET_REG1 A = 0x15 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004F = E TEST_BIT 0 = bool(0x004F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004F = E TEST_BIT 0 = bool(0x004F & 0x0080) REG 0x0064 = temp0 REG 0x004F = E SUB1 0x15 = 0x64 - 0x4F TEST_BIT 0 = bool(0x0015 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x004F = E SUB1 0x15 = 0x64 - 0x4F TEST_BIT 0 = bool(0x0015 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0009 = C SET_REG1 A = 0x09 temp2.b = A ---------------- REG 0x0009 = A SET_REG1 temp2 = 0x09 A = A + E ---------------- REG 0x0009 = A REG 0x004F = E ADD1 0x58 = 0x09 + 0x4F SET_REG1 A = 0x58 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0009 = temp2 REG 0x004F = E SUB1 0xB0 = 0xFF - 0x4F CMP_UGT 0 = 0x0009 > 0x00B0 SET_FLAG c = 0 C = A ---------------- REG 0x0058 = A SET_REG1 C = 0x58 A = B ---------------- REG 0x000C = B SET_REG1 A = 0x0C A = adc.b(A, D, flag:c) ---------------- REG 0x000C = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000C = 0x000C + 0x0000 + 0 SET_REG1 A = 0x0C B = A ---------------- REG 0x000C = A SET_REG1 B = 0x0C DE = DE + 1 ---------------- REG 0x004F = DE ADD2 0x0050 = 0x004F + 0x0001 SET_REG2 DE = 0x0050 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0050 = E SUB1 0x14 = 0x64 - 0x50 SET_REG1 A = 0x14 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0050 = E TEST_BIT 0 = bool(0x0050 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0050 = E TEST_BIT 0 = bool(0x0050 & 0x0080) REG 0x0064 = temp0 REG 0x0050 = E SUB1 0x14 = 0x64 - 0x50 TEST_BIT 0 = bool(0x0014 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0050 = E SUB1 0x14 = 0x64 - 0x50 TEST_BIT 0 = bool(0x0014 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0058 = C SET_REG1 A = 0x58 temp2.b = A ---------------- REG 0x0058 = A SET_REG1 temp2 = 0x58 A = A + E ---------------- REG 0x0058 = A REG 0x0050 = E ADD1 0xA8 = 0x58 + 0x50 SET_REG1 A = 0xA8 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0058 = temp2 REG 0x0050 = E SUB1 0xAF = 0xFF - 0x50 CMP_UGT 0 = 0x0058 > 0x00AF SET_FLAG c = 0 C = A ---------------- REG 0x00A8 = A SET_REG1 C = 0xA8 A = B ---------------- REG 0x000C = B SET_REG1 A = 0x0C A = adc.b(A, D, flag:c) ---------------- REG 0x000C = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000C = 0x000C + 0x0000 + 0 SET_REG1 A = 0x0C B = A ---------------- REG 0x000C = A SET_REG1 B = 0x0C DE = DE + 1 ---------------- REG 0x0050 = DE ADD2 0x0051 = 0x0050 + 0x0001 SET_REG2 DE = 0x0051 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0051 = E SUB1 0x13 = 0x64 - 0x51 SET_REG1 A = 0x13 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0051 = E TEST_BIT 0 = bool(0x0051 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0051 = E TEST_BIT 0 = bool(0x0051 & 0x0080) REG 0x0064 = temp0 REG 0x0051 = E SUB1 0x13 = 0x64 - 0x51 TEST_BIT 0 = bool(0x0013 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0051 = E SUB1 0x13 = 0x64 - 0x51 TEST_BIT 0 = bool(0x0013 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00A8 = C SET_REG1 A = 0xA8 temp2.b = A ---------------- REG 0x00A8 = A SET_REG1 temp2 = 0xA8 A = A + E ---------------- REG 0x00A8 = A REG 0x0051 = E ADD1 0xF9 = 0xA8 + 0x51 SET_REG1 A = 0xF9 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00A8 = temp2 REG 0x0051 = E SUB1 0xAE = 0xFF - 0x51 CMP_UGT 0 = 0x00A8 > 0x00AE SET_FLAG c = 0 C = A ---------------- REG 0x00F9 = A SET_REG1 C = 0xF9 A = B ---------------- REG 0x000C = B SET_REG1 A = 0x0C A = adc.b(A, D, flag:c) ---------------- REG 0x000C = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000C = 0x000C + 0x0000 + 0 SET_REG1 A = 0x0C B = A ---------------- REG 0x000C = A SET_REG1 B = 0x0C DE = DE + 1 ---------------- REG 0x0051 = DE ADD2 0x0052 = 0x0051 + 0x0001 SET_REG2 DE = 0x0052 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0052 = E SUB1 0x12 = 0x64 - 0x52 SET_REG1 A = 0x12 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0052 = E TEST_BIT 0 = bool(0x0052 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0052 = E TEST_BIT 0 = bool(0x0052 & 0x0080) REG 0x0064 = temp0 REG 0x0052 = E SUB1 0x12 = 0x64 - 0x52 TEST_BIT 0 = bool(0x0012 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0052 = E SUB1 0x12 = 0x64 - 0x52 TEST_BIT 0 = bool(0x0012 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00F9 = C SET_REG1 A = 0xF9 temp2.b = A ---------------- REG 0x00F9 = A SET_REG1 temp2 = 0xF9 A = A + E ---------------- REG 0x00F9 = A REG 0x0052 = E ADD1 0x4B = 0xF9 + 0x52 SET_REG1 A = 0x4B flag:c = temp2.b u> 0xff - E ---------------- REG 0x00F9 = temp2 REG 0x0052 = E SUB1 0xAD = 0xFF - 0x52 CMP_UGT 1 = 0x00F9 > 0x00AD SET_FLAG c = 1 C = A ---------------- REG 0x004B = A SET_REG1 C = 0x4B A = B ---------------- REG 0x000C = B SET_REG1 A = 0x0C A = adc.b(A, D, flag:c) ---------------- REG 0x000C = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000D = 0x000C + 0x0000 + 1 SET_REG1 A = 0x0D B = A ---------------- REG 0x000D = A SET_REG1 B = 0x0D DE = DE + 1 ---------------- REG 0x0052 = DE ADD2 0x0053 = 0x0052 + 0x0001 SET_REG2 DE = 0x0053 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0053 = E SUB1 0x11 = 0x64 - 0x53 SET_REG1 A = 0x11 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0053 = E TEST_BIT 0 = bool(0x0053 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0053 = E TEST_BIT 0 = bool(0x0053 & 0x0080) REG 0x0064 = temp0 REG 0x0053 = E SUB1 0x11 = 0x64 - 0x53 TEST_BIT 0 = bool(0x0011 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0053 = E SUB1 0x11 = 0x64 - 0x53 TEST_BIT 0 = bool(0x0011 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x004B = C SET_REG1 A = 0x4B temp2.b = A ---------------- REG 0x004B = A SET_REG1 temp2 = 0x4B A = A + E ---------------- REG 0x004B = A REG 0x0053 = E ADD1 0x9E = 0x4B + 0x53 SET_REG1 A = 0x9E flag:c = temp2.b u> 0xff - E ---------------- REG 0x004B = temp2 REG 0x0053 = E SUB1 0xAC = 0xFF - 0x53 CMP_UGT 0 = 0x004B > 0x00AC SET_FLAG c = 0 C = A ---------------- REG 0x009E = A SET_REG1 C = 0x9E A = B ---------------- REG 0x000D = B SET_REG1 A = 0x0D A = adc.b(A, D, flag:c) ---------------- REG 0x000D = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000D = 0x000D + 0x0000 + 0 SET_REG1 A = 0x0D B = A ---------------- REG 0x000D = A SET_REG1 B = 0x0D DE = DE + 1 ---------------- REG 0x0053 = DE ADD2 0x0054 = 0x0053 + 0x0001 SET_REG2 DE = 0x0054 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0054 = E SUB1 0x10 = 0x64 - 0x54 SET_REG1 A = 0x10 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0054 = E TEST_BIT 0 = bool(0x0054 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0054 = E TEST_BIT 0 = bool(0x0054 & 0x0080) REG 0x0064 = temp0 REG 0x0054 = E SUB1 0x10 = 0x64 - 0x54 TEST_BIT 0 = bool(0x0010 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0054 = E SUB1 0x10 = 0x64 - 0x54 TEST_BIT 0 = bool(0x0010 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x009E = C SET_REG1 A = 0x9E temp2.b = A ---------------- REG 0x009E = A SET_REG1 temp2 = 0x9E A = A + E ---------------- REG 0x009E = A REG 0x0054 = E ADD1 0xF2 = 0x9E + 0x54 SET_REG1 A = 0xF2 flag:c = temp2.b u> 0xff - E ---------------- REG 0x009E = temp2 REG 0x0054 = E SUB1 0xAB = 0xFF - 0x54 CMP_UGT 0 = 0x009E > 0x00AB SET_FLAG c = 0 C = A ---------------- REG 0x00F2 = A SET_REG1 C = 0xF2 A = B ---------------- REG 0x000D = B SET_REG1 A = 0x0D A = adc.b(A, D, flag:c) ---------------- REG 0x000D = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000D = 0x000D + 0x0000 + 0 SET_REG1 A = 0x0D B = A ---------------- REG 0x000D = A SET_REG1 B = 0x0D DE = DE + 1 ---------------- REG 0x0054 = DE ADD2 0x0055 = 0x0054 + 0x0001 SET_REG2 DE = 0x0055 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0055 = E SUB1 0x0F = 0x64 - 0x55 SET_REG1 A = 0x0F flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0055 = E TEST_BIT 0 = bool(0x0055 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0055 = E TEST_BIT 0 = bool(0x0055 & 0x0080) REG 0x0064 = temp0 REG 0x0055 = E SUB1 0x0F = 0x64 - 0x55 TEST_BIT 0 = bool(0x000F & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0055 = E SUB1 0x0F = 0x64 - 0x55 TEST_BIT 0 = bool(0x000F & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00F2 = C SET_REG1 A = 0xF2 temp2.b = A ---------------- REG 0x00F2 = A SET_REG1 temp2 = 0xF2 A = A + E ---------------- REG 0x00F2 = A REG 0x0055 = E ADD1 0x47 = 0xF2 + 0x55 SET_REG1 A = 0x47 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00F2 = temp2 REG 0x0055 = E SUB1 0xAA = 0xFF - 0x55 CMP_UGT 1 = 0x00F2 > 0x00AA SET_FLAG c = 1 C = A ---------------- REG 0x0047 = A SET_REG1 C = 0x47 A = B ---------------- REG 0x000D = B SET_REG1 A = 0x0D A = adc.b(A, D, flag:c) ---------------- REG 0x000D = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000E = 0x000D + 0x0000 + 1 SET_REG1 A = 0x0E B = A ---------------- REG 0x000E = A SET_REG1 B = 0x0E DE = DE + 1 ---------------- REG 0x0055 = DE ADD2 0x0056 = 0x0055 + 0x0001 SET_REG2 DE = 0x0056 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0056 = E SUB1 0x0E = 0x64 - 0x56 SET_REG1 A = 0x0E flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0056 = E TEST_BIT 0 = bool(0x0056 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0056 = E TEST_BIT 0 = bool(0x0056 & 0x0080) REG 0x0064 = temp0 REG 0x0056 = E SUB1 0x0E = 0x64 - 0x56 TEST_BIT 0 = bool(0x000E & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0056 = E SUB1 0x0E = 0x64 - 0x56 TEST_BIT 0 = bool(0x000E & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0047 = C SET_REG1 A = 0x47 temp2.b = A ---------------- REG 0x0047 = A SET_REG1 temp2 = 0x47 A = A + E ---------------- REG 0x0047 = A REG 0x0056 = E ADD1 0x9D = 0x47 + 0x56 SET_REG1 A = 0x9D flag:c = temp2.b u> 0xff - E ---------------- REG 0x0047 = temp2 REG 0x0056 = E SUB1 0xA9 = 0xFF - 0x56 CMP_UGT 0 = 0x0047 > 0x00A9 SET_FLAG c = 0 C = A ---------------- REG 0x009D = A SET_REG1 C = 0x9D A = B ---------------- REG 0x000E = B SET_REG1 A = 0x0E A = adc.b(A, D, flag:c) ---------------- REG 0x000E = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000E = 0x000E + 0x0000 + 0 SET_REG1 A = 0x0E B = A ---------------- REG 0x000E = A SET_REG1 B = 0x0E DE = DE + 1 ---------------- REG 0x0056 = DE ADD2 0x0057 = 0x0056 + 0x0001 SET_REG2 DE = 0x0057 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0057 = E SUB1 0x0D = 0x64 - 0x57 SET_REG1 A = 0x0D flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0057 = E TEST_BIT 0 = bool(0x0057 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0057 = E TEST_BIT 0 = bool(0x0057 & 0x0080) REG 0x0064 = temp0 REG 0x0057 = E SUB1 0x0D = 0x64 - 0x57 TEST_BIT 0 = bool(0x000D & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0057 = E SUB1 0x0D = 0x64 - 0x57 TEST_BIT 0 = bool(0x000D & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x009D = C SET_REG1 A = 0x9D temp2.b = A ---------------- REG 0x009D = A SET_REG1 temp2 = 0x9D A = A + E ---------------- REG 0x009D = A REG 0x0057 = E ADD1 0xF4 = 0x9D + 0x57 SET_REG1 A = 0xF4 flag:c = temp2.b u> 0xff - E ---------------- REG 0x009D = temp2 REG 0x0057 = E SUB1 0xA8 = 0xFF - 0x57 CMP_UGT 0 = 0x009D > 0x00A8 SET_FLAG c = 0 C = A ---------------- REG 0x00F4 = A SET_REG1 C = 0xF4 A = B ---------------- REG 0x000E = B SET_REG1 A = 0x0E A = adc.b(A, D, flag:c) ---------------- REG 0x000E = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000E = 0x000E + 0x0000 + 0 SET_REG1 A = 0x0E B = A ---------------- REG 0x000E = A SET_REG1 B = 0x0E DE = DE + 1 ---------------- REG 0x0057 = DE ADD2 0x0058 = 0x0057 + 0x0001 SET_REG2 DE = 0x0058 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0058 = E SUB1 0x0C = 0x64 - 0x58 SET_REG1 A = 0x0C flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0058 = E TEST_BIT 0 = bool(0x0058 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0058 = E TEST_BIT 0 = bool(0x0058 & 0x0080) REG 0x0064 = temp0 REG 0x0058 = E SUB1 0x0C = 0x64 - 0x58 TEST_BIT 0 = bool(0x000C & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0058 = E SUB1 0x0C = 0x64 - 0x58 TEST_BIT 0 = bool(0x000C & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00F4 = C SET_REG1 A = 0xF4 temp2.b = A ---------------- REG 0x00F4 = A SET_REG1 temp2 = 0xF4 A = A + E ---------------- REG 0x00F4 = A REG 0x0058 = E ADD1 0x4C = 0xF4 + 0x58 SET_REG1 A = 0x4C flag:c = temp2.b u> 0xff - E ---------------- REG 0x00F4 = temp2 REG 0x0058 = E SUB1 0xA7 = 0xFF - 0x58 CMP_UGT 1 = 0x00F4 > 0x00A7 SET_FLAG c = 1 C = A ---------------- REG 0x004C = A SET_REG1 C = 0x4C A = B ---------------- REG 0x000E = B SET_REG1 A = 0x0E A = adc.b(A, D, flag:c) ---------------- REG 0x000E = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000F = 0x000E + 0x0000 + 1 SET_REG1 A = 0x0F B = A ---------------- REG 0x000F = A SET_REG1 B = 0x0F DE = DE + 1 ---------------- REG 0x0058 = DE ADD2 0x0059 = 0x0058 + 0x0001 SET_REG2 DE = 0x0059 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0059 = E SUB1 0x0B = 0x64 - 0x59 SET_REG1 A = 0x0B flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0059 = E TEST_BIT 0 = bool(0x0059 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0059 = E TEST_BIT 0 = bool(0x0059 & 0x0080) REG 0x0064 = temp0 REG 0x0059 = E SUB1 0x0B = 0x64 - 0x59 TEST_BIT 0 = bool(0x000B & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0059 = E SUB1 0x0B = 0x64 - 0x59 TEST_BIT 0 = bool(0x000B & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x004C = C SET_REG1 A = 0x4C temp2.b = A ---------------- REG 0x004C = A SET_REG1 temp2 = 0x4C A = A + E ---------------- REG 0x004C = A REG 0x0059 = E ADD1 0xA5 = 0x4C + 0x59 SET_REG1 A = 0xA5 flag:c = temp2.b u> 0xff - E ---------------- REG 0x004C = temp2 REG 0x0059 = E SUB1 0xA6 = 0xFF - 0x59 CMP_UGT 0 = 0x004C > 0x00A6 SET_FLAG c = 0 C = A ---------------- REG 0x00A5 = A SET_REG1 C = 0xA5 A = B ---------------- REG 0x000F = B SET_REG1 A = 0x0F A = adc.b(A, D, flag:c) ---------------- REG 0x000F = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000F = 0x000F + 0x0000 + 0 SET_REG1 A = 0x0F B = A ---------------- REG 0x000F = A SET_REG1 B = 0x0F DE = DE + 1 ---------------- REG 0x0059 = DE ADD2 0x005A = 0x0059 + 0x0001 SET_REG2 DE = 0x005A goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x005A = E SUB1 0x0A = 0x64 - 0x5A SET_REG1 A = 0x0A flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005A = E TEST_BIT 0 = bool(0x005A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005A = E TEST_BIT 0 = bool(0x005A & 0x0080) REG 0x0064 = temp0 REG 0x005A = E SUB1 0x0A = 0x64 - 0x5A TEST_BIT 0 = bool(0x000A & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x005A = E SUB1 0x0A = 0x64 - 0x5A TEST_BIT 0 = bool(0x000A & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00A5 = C SET_REG1 A = 0xA5 temp2.b = A ---------------- REG 0x00A5 = A SET_REG1 temp2 = 0xA5 A = A + E ---------------- REG 0x00A5 = A REG 0x005A = E ADD1 0xFF = 0xA5 + 0x5A SET_REG1 A = 0xFF flag:c = temp2.b u> 0xff - E ---------------- REG 0x00A5 = temp2 REG 0x005A = E SUB1 0xA5 = 0xFF - 0x5A CMP_UGT 0 = 0x00A5 > 0x00A5 SET_FLAG c = 0 C = A ---------------- REG 0x00FF = A SET_REG1 C = 0xFF A = B ---------------- REG 0x000F = B SET_REG1 A = 0x0F A = adc.b(A, D, flag:c) ---------------- REG 0x000F = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000F = 0x000F + 0x0000 + 0 SET_REG1 A = 0x0F B = A ---------------- REG 0x000F = A SET_REG1 B = 0x0F DE = DE + 1 ---------------- REG 0x005A = DE ADD2 0x005B = 0x005A + 0x0001 SET_REG2 DE = 0x005B goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x005B = E SUB1 0x09 = 0x64 - 0x5B SET_REG1 A = 0x09 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005B = E TEST_BIT 0 = bool(0x005B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005B = E TEST_BIT 0 = bool(0x005B & 0x0080) REG 0x0064 = temp0 REG 0x005B = E SUB1 0x09 = 0x64 - 0x5B TEST_BIT 0 = bool(0x0009 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x005B = E SUB1 0x09 = 0x64 - 0x5B TEST_BIT 0 = bool(0x0009 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00FF = C SET_REG1 A = 0xFF temp2.b = A ---------------- REG 0x00FF = A SET_REG1 temp2 = 0xFF A = A + E ---------------- REG 0x00FF = A REG 0x005B = E ADD1 0x5A = 0xFF + 0x5B SET_REG1 A = 0x5A flag:c = temp2.b u> 0xff - E ---------------- REG 0x00FF = temp2 REG 0x005B = E SUB1 0xA4 = 0xFF - 0x5B CMP_UGT 1 = 0x00FF > 0x00A4 SET_FLAG c = 1 C = A ---------------- REG 0x005A = A SET_REG1 C = 0x5A A = B ---------------- REG 0x000F = B SET_REG1 A = 0x0F A = adc.b(A, D, flag:c) ---------------- REG 0x000F = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0010 = 0x000F + 0x0000 + 1 SET_REG1 A = 0x10 B = A ---------------- REG 0x0010 = A SET_REG1 B = 0x10 DE = DE + 1 ---------------- REG 0x005B = DE ADD2 0x005C = 0x005B + 0x0001 SET_REG2 DE = 0x005C goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x005C = E SUB1 0x08 = 0x64 - 0x5C SET_REG1 A = 0x08 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005C = E TEST_BIT 0 = bool(0x005C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005C = E TEST_BIT 0 = bool(0x005C & 0x0080) REG 0x0064 = temp0 REG 0x005C = E SUB1 0x08 = 0x64 - 0x5C TEST_BIT 0 = bool(0x0008 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x005C = E SUB1 0x08 = 0x64 - 0x5C TEST_BIT 0 = bool(0x0008 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x005A = C SET_REG1 A = 0x5A temp2.b = A ---------------- REG 0x005A = A SET_REG1 temp2 = 0x5A A = A + E ---------------- REG 0x005A = A REG 0x005C = E ADD1 0xB6 = 0x5A + 0x5C SET_REG1 A = 0xB6 flag:c = temp2.b u> 0xff - E ---------------- REG 0x005A = temp2 REG 0x005C = E SUB1 0xA3 = 0xFF - 0x5C CMP_UGT 0 = 0x005A > 0x00A3 SET_FLAG c = 0 C = A ---------------- REG 0x00B6 = A SET_REG1 C = 0xB6 A = B ---------------- REG 0x0010 = B SET_REG1 A = 0x10 A = adc.b(A, D, flag:c) ---------------- REG 0x0010 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0010 = 0x0010 + 0x0000 + 0 SET_REG1 A = 0x10 B = A ---------------- REG 0x0010 = A SET_REG1 B = 0x10 DE = DE + 1 ---------------- REG 0x005C = DE ADD2 0x005D = 0x005C + 0x0001 SET_REG2 DE = 0x005D goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x005D = E SUB1 0x07 = 0x64 - 0x5D SET_REG1 A = 0x07 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005D = E TEST_BIT 0 = bool(0x005D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005D = E TEST_BIT 0 = bool(0x005D & 0x0080) REG 0x0064 = temp0 REG 0x005D = E SUB1 0x07 = 0x64 - 0x5D TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x005D = E SUB1 0x07 = 0x64 - 0x5D TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00B6 = C SET_REG1 A = 0xB6 temp2.b = A ---------------- REG 0x00B6 = A SET_REG1 temp2 = 0xB6 A = A + E ---------------- REG 0x00B6 = A REG 0x005D = E ADD1 0x13 = 0xB6 + 0x5D SET_REG1 A = 0x13 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00B6 = temp2 REG 0x005D = E SUB1 0xA2 = 0xFF - 0x5D CMP_UGT 1 = 0x00B6 > 0x00A2 SET_FLAG c = 1 C = A ---------------- REG 0x0013 = A SET_REG1 C = 0x13 A = B ---------------- REG 0x0010 = B SET_REG1 A = 0x10 A = adc.b(A, D, flag:c) ---------------- REG 0x0010 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0011 = 0x0010 + 0x0000 + 1 SET_REG1 A = 0x11 B = A ---------------- REG 0x0011 = A SET_REG1 B = 0x11 DE = DE + 1 ---------------- REG 0x005D = DE ADD2 0x005E = 0x005D + 0x0001 SET_REG2 DE = 0x005E goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x005E = E SUB1 0x06 = 0x64 - 0x5E SET_REG1 A = 0x06 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005E = E TEST_BIT 0 = bool(0x005E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005E = E TEST_BIT 0 = bool(0x005E & 0x0080) REG 0x0064 = temp0 REG 0x005E = E SUB1 0x06 = 0x64 - 0x5E TEST_BIT 0 = bool(0x0006 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x005E = E SUB1 0x06 = 0x64 - 0x5E TEST_BIT 0 = bool(0x0006 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0013 = C SET_REG1 A = 0x13 temp2.b = A ---------------- REG 0x0013 = A SET_REG1 temp2 = 0x13 A = A + E ---------------- REG 0x0013 = A REG 0x005E = E ADD1 0x71 = 0x13 + 0x5E SET_REG1 A = 0x71 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0013 = temp2 REG 0x005E = E SUB1 0xA1 = 0xFF - 0x5E CMP_UGT 0 = 0x0013 > 0x00A1 SET_FLAG c = 0 C = A ---------------- REG 0x0071 = A SET_REG1 C = 0x71 A = B ---------------- REG 0x0011 = B SET_REG1 A = 0x11 A = adc.b(A, D, flag:c) ---------------- REG 0x0011 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0011 = 0x0011 + 0x0000 + 0 SET_REG1 A = 0x11 B = A ---------------- REG 0x0011 = A SET_REG1 B = 0x11 DE = DE + 1 ---------------- REG 0x005E = DE ADD2 0x005F = 0x005E + 0x0001 SET_REG2 DE = 0x005F goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x005F = E SUB1 0x05 = 0x64 - 0x5F SET_REG1 A = 0x05 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005F = E TEST_BIT 0 = bool(0x005F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005F = E TEST_BIT 0 = bool(0x005F & 0x0080) REG 0x0064 = temp0 REG 0x005F = E SUB1 0x05 = 0x64 - 0x5F TEST_BIT 0 = bool(0x0005 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x005F = E SUB1 0x05 = 0x64 - 0x5F TEST_BIT 0 = bool(0x0005 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0071 = C SET_REG1 A = 0x71 temp2.b = A ---------------- REG 0x0071 = A SET_REG1 temp2 = 0x71 A = A + E ---------------- REG 0x0071 = A REG 0x005F = E ADD1 0xD0 = 0x71 + 0x5F SET_REG1 A = 0xD0 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0071 = temp2 REG 0x005F = E SUB1 0xA0 = 0xFF - 0x5F CMP_UGT 0 = 0x0071 > 0x00A0 SET_FLAG c = 0 C = A ---------------- REG 0x00D0 = A SET_REG1 C = 0xD0 A = B ---------------- REG 0x0011 = B SET_REG1 A = 0x11 A = adc.b(A, D, flag:c) ---------------- REG 0x0011 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0011 = 0x0011 + 0x0000 + 0 SET_REG1 A = 0x11 B = A ---------------- REG 0x0011 = A SET_REG1 B = 0x11 DE = DE + 1 ---------------- REG 0x005F = DE ADD2 0x0060 = 0x005F + 0x0001 SET_REG2 DE = 0x0060 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0060 = E SUB1 0x04 = 0x64 - 0x60 SET_REG1 A = 0x04 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0060 = E TEST_BIT 0 = bool(0x0060 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0060 = E TEST_BIT 0 = bool(0x0060 & 0x0080) REG 0x0064 = temp0 REG 0x0060 = E SUB1 0x04 = 0x64 - 0x60 TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0060 = E SUB1 0x04 = 0x64 - 0x60 TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00D0 = C SET_REG1 A = 0xD0 temp2.b = A ---------------- REG 0x00D0 = A SET_REG1 temp2 = 0xD0 A = A + E ---------------- REG 0x00D0 = A REG 0x0060 = E ADD1 0x30 = 0xD0 + 0x60 SET_REG1 A = 0x30 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00D0 = temp2 REG 0x0060 = E SUB1 0x9F = 0xFF - 0x60 CMP_UGT 1 = 0x00D0 > 0x009F SET_FLAG c = 1 C = A ---------------- REG 0x0030 = A SET_REG1 C = 0x30 A = B ---------------- REG 0x0011 = B SET_REG1 A = 0x11 A = adc.b(A, D, flag:c) ---------------- REG 0x0011 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0012 = 0x0011 + 0x0000 + 1 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE + 1 ---------------- REG 0x0060 = DE ADD2 0x0061 = 0x0060 + 0x0001 SET_REG2 DE = 0x0061 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0061 = E SUB1 0x03 = 0x64 - 0x61 SET_REG1 A = 0x03 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0061 = E TEST_BIT 0 = bool(0x0061 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0061 = E TEST_BIT 0 = bool(0x0061 & 0x0080) REG 0x0064 = temp0 REG 0x0061 = E SUB1 0x03 = 0x64 - 0x61 TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0061 = E SUB1 0x03 = 0x64 - 0x61 TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0030 = C SET_REG1 A = 0x30 temp2.b = A ---------------- REG 0x0030 = A SET_REG1 temp2 = 0x30 A = A + E ---------------- REG 0x0030 = A REG 0x0061 = E ADD1 0x91 = 0x30 + 0x61 SET_REG1 A = 0x91 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0030 = temp2 REG 0x0061 = E SUB1 0x9E = 0xFF - 0x61 CMP_UGT 0 = 0x0030 > 0x009E SET_FLAG c = 0 C = A ---------------- REG 0x0091 = A SET_REG1 C = 0x91 A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE + 1 ---------------- REG 0x0061 = DE ADD2 0x0062 = 0x0061 + 0x0001 SET_REG2 DE = 0x0062 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0062 = E SUB1 0x02 = 0x64 - 0x62 SET_REG1 A = 0x02 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0062 = E TEST_BIT 0 = bool(0x0062 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0062 = E TEST_BIT 0 = bool(0x0062 & 0x0080) REG 0x0064 = temp0 REG 0x0062 = E SUB1 0x02 = 0x64 - 0x62 TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0062 = E SUB1 0x02 = 0x64 - 0x62 TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0091 = C SET_REG1 A = 0x91 temp2.b = A ---------------- REG 0x0091 = A SET_REG1 temp2 = 0x91 A = A + E ---------------- REG 0x0091 = A REG 0x0062 = E ADD1 0xF3 = 0x91 + 0x62 SET_REG1 A = 0xF3 flag:c = temp2.b u> 0xff - E ---------------- REG 0x0091 = temp2 REG 0x0062 = E SUB1 0x9D = 0xFF - 0x62 CMP_UGT 0 = 0x0091 > 0x009D SET_FLAG c = 0 C = A ---------------- REG 0x00F3 = A SET_REG1 C = 0xF3 A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE + 1 ---------------- REG 0x0062 = DE ADD2 0x0063 = 0x0062 + 0x0001 SET_REG2 DE = 0x0063 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0063 = E SUB1 0x01 = 0x64 - 0x63 SET_REG1 A = 0x01 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0063 = E TEST_BIT 0 = bool(0x0063 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0063 = E TEST_BIT 0 = bool(0x0063 & 0x0080) REG 0x0064 = temp0 REG 0x0063 = E SUB1 0x01 = 0x64 - 0x63 TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0063 = E SUB1 0x01 = 0x64 - 0x63 TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x00F3 = C SET_REG1 A = 0xF3 temp2.b = A ---------------- REG 0x00F3 = A SET_REG1 temp2 = 0xF3 A = A + E ---------------- REG 0x00F3 = A REG 0x0063 = E ADD1 0x56 = 0xF3 + 0x63 SET_REG1 A = 0x56 flag:c = temp2.b u> 0xff - E ---------------- REG 0x00F3 = temp2 REG 0x0063 = E SUB1 0x9C = 0xFF - 0x63 CMP_UGT 1 = 0x00F3 > 0x009C SET_FLAG c = 1 C = A ---------------- REG 0x0056 = A SET_REG1 C = 0x56 A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0013 = 0x0012 + 0x0000 + 1 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE + 1 ---------------- REG 0x0063 = DE ADD2 0x0064 = 0x0063 + 0x0001 SET_REG2 DE = 0x0064 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0064 = E SUB1 0x00 = 0x64 - 0x64 SET_REG1 A = 0x00 flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0064 = E TEST_BIT 0 = bool(0x0064 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0064 = E TEST_BIT 0 = bool(0x0064 & 0x0080) REG 0x0064 = temp0 REG 0x0064 = E SUB1 0x00 = 0x64 - 0x64 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0064 = E SUB1 0x00 = 0x64 - 0x64 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 0 = vm_flags[s] goto 24 @ 0x2fd ---------------- A = C ---------------- REG 0x0056 = C SET_REG1 A = 0x56 temp2.b = A ---------------- REG 0x0056 = A SET_REG1 temp2 = 0x56 A = A + E ---------------- REG 0x0056 = A REG 0x0064 = E ADD1 0xBA = 0x56 + 0x64 SET_REG1 A = 0xBA flag:c = temp2.b u> 0xff - E ---------------- REG 0x0056 = temp2 REG 0x0064 = E SUB1 0x9B = 0xFF - 0x64 CMP_UGT 0 = 0x0056 > 0x009B SET_FLAG c = 0 C = A ---------------- REG 0x00BA = A SET_REG1 C = 0xBA A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE + 1 ---------------- REG 0x0064 = DE ADD2 0x0065 = 0x0064 + 0x0001 SET_REG2 DE = 0x0065 goto 3 @ 0x2ec ---------------- HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE A = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 A = 0x64 temp0.b = A ---------------- REG 0x0064 = A SET_REG1 temp0 = 0x64 A = A - E ---------------- REG 0x0064 = A REG 0x0065 = E SUB1 0xFF = 0x64 - 0x65 SET_REG1 A = 0xFF flag:c = (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(temp0.b - E, 0x80))) | (test_bit(temp0.b - E, 0x80) & (test_bit(temp0.b, 0x80) ^ 0x1)) ---------------- REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0065 = E TEST_BIT 0 = bool(0x0065 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0065 = E TEST_BIT 0 = bool(0x0065 & 0x0080) REG 0x0064 = temp0 REG 0x0065 = E SUB1 0xFF = 0x64 - 0x65 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0064 = temp0 REG 0x0065 = E SUB1 0xFF = 0x64 - 0x65 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0064 = temp0 TEST_BIT 0 = bool(0x0064 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF A = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = sbb.b(temp1.b, D, flag:c) ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp1.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp1.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp1.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp1.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp1.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp1 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp1 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 16 @ 0x2fa else 17 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s) then 18 @ 0x306 else 21 ---------------- FLAG 1 = vm_flags[s] L = C ---------------- REG 0x00BA = C SET_REG1 L = 0xBA H = B ---------------- REG 0x0013 = B SET_REG1 H = 0x13 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m triangle_up(100) (5050 is correct) BC = 0 ---------------- SET_REG2 BC = 0x0000 HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE E = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x4 = mem[0x07FE] SET_REG1 E = 0x04 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF D = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 D = 0x00 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 TEST_BIT 1 = bool(0x00FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 TEST_BIT 1 = bool(0x00FC & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0000 = C SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = A + E ---------------- REG 0x0000 = A REG 0x0004 = E ADD1 0x04 = 0x00 + 0x04 SET_REG1 A = 0x04 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0000 = temp1 REG 0x0004 = E SUB1 0xFB = 0xFF - 0x04 CMP_UGT 0 = 0x0000 > 0x00FB SET_FLAG c = 0 C = A ---------------- REG 0x0004 = A SET_REG1 C = 0x04 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0004 = DE SUB2 0x0003 = 0x0004 - 0x0001 SET_REG2 DE = 0x0003 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 TEST_BIT 1 = bool(0x00FD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 TEST_BIT 1 = bool(0x00FD & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0004 = C SET_REG1 A = 0x04 temp1.b = A ---------------- REG 0x0004 = A SET_REG1 temp1 = 0x04 A = A + E ---------------- REG 0x0004 = A REG 0x0003 = E ADD1 0x07 = 0x04 + 0x03 SET_REG1 A = 0x07 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0004 = temp1 REG 0x0003 = E SUB1 0xFC = 0xFF - 0x03 CMP_UGT 0 = 0x0004 > 0x00FC SET_FLAG c = 0 C = A ---------------- REG 0x0007 = A SET_REG1 C = 0x07 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0003 = DE SUB2 0x0002 = 0x0003 - 0x0001 SET_REG2 DE = 0x0002 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 TEST_BIT 1 = bool(0x00FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 TEST_BIT 1 = bool(0x00FE & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0007 = C SET_REG1 A = 0x07 temp1.b = A ---------------- REG 0x0007 = A SET_REG1 temp1 = 0x07 A = A + E ---------------- REG 0x0007 = A REG 0x0002 = E ADD1 0x09 = 0x07 + 0x02 SET_REG1 A = 0x09 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0007 = temp1 REG 0x0002 = E SUB1 0xFD = 0xFF - 0x02 CMP_UGT 0 = 0x0007 > 0x00FD SET_FLAG c = 0 C = A ---------------- REG 0x0009 = A SET_REG1 C = 0x09 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0002 = DE SUB2 0x0001 = 0x0002 - 0x0001 SET_REG2 DE = 0x0001 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0009 = C SET_REG1 A = 0x09 temp1.b = A ---------------- REG 0x0009 = A SET_REG1 temp1 = 0x09 A = A + E ---------------- REG 0x0009 = A REG 0x0001 = E ADD1 0x0A = 0x09 + 0x01 SET_REG1 A = 0x0A flag:c = temp1.b u> 0xff - E ---------------- REG 0x0009 = temp1 REG 0x0001 = E SUB1 0xFE = 0xFF - 0x01 CMP_UGT 0 = 0x0009 > 0x00FE SET_FLAG c = 0 C = A ---------------- REG 0x000A = A SET_REG1 C = 0x0A A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0001 = DE SUB2 0x0000 = 0x0001 - 0x0001 SET_REG2 DE = 0x0000 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = E TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = E TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 0 = vm_flags[s] XOR 0x0001 = 0x0000 ^ 0x0001 L = C ---------------- REG 0x000A = C SET_REG1 L = 0x0A H = B ---------------- REG 0x0000 = B SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m triangle_down(4) (10 is correct) BC = 0 ---------------- SET_REG2 BC = 0x0000 HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE E = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x7 = mem[0x07FE] SET_REG1 E = 0x07 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF D = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 D = 0x00 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0007 = E SUB1 0xF9 = 0x00 - 0x07 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x0000 = A REG 0x0007 = E SUB1 0xF9 = 0x00 - 0x07 TEST_BIT 1 = bool(0x00F9 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0007 = E SUB1 0xF9 = 0x00 - 0x07 TEST_BIT 1 = bool(0x00F9 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0000 = C SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = A + E ---------------- REG 0x0000 = A REG 0x0007 = E ADD1 0x07 = 0x00 + 0x07 SET_REG1 A = 0x07 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0000 = temp1 REG 0x0007 = E SUB1 0xF8 = 0xFF - 0x07 CMP_UGT 0 = 0x0000 > 0x00F8 SET_FLAG c = 0 C = A ---------------- REG 0x0007 = A SET_REG1 C = 0x07 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0007 = DE SUB2 0x0006 = 0x0007 - 0x0001 SET_REG2 DE = 0x0006 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0006 = E SUB1 0xFA = 0x00 - 0x06 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) REG 0x0000 = A REG 0x0006 = E SUB1 0xFA = 0x00 - 0x06 TEST_BIT 1 = bool(0x00FA & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0006 = E SUB1 0xFA = 0x00 - 0x06 TEST_BIT 1 = bool(0x00FA & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0007 = C SET_REG1 A = 0x07 temp1.b = A ---------------- REG 0x0007 = A SET_REG1 temp1 = 0x07 A = A + E ---------------- REG 0x0007 = A REG 0x0006 = E ADD1 0x0D = 0x07 + 0x06 SET_REG1 A = 0x0D flag:c = temp1.b u> 0xff - E ---------------- REG 0x0007 = temp1 REG 0x0006 = E SUB1 0xF9 = 0xFF - 0x06 CMP_UGT 0 = 0x0007 > 0x00F9 SET_FLAG c = 0 C = A ---------------- REG 0x000D = A SET_REG1 C = 0x0D A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0006 = DE SUB2 0x0005 = 0x0006 - 0x0001 SET_REG2 DE = 0x0005 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0005 = E SUB1 0xFB = 0x00 - 0x05 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) REG 0x0000 = A REG 0x0005 = E SUB1 0xFB = 0x00 - 0x05 TEST_BIT 1 = bool(0x00FB & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0005 = E SUB1 0xFB = 0x00 - 0x05 TEST_BIT 1 = bool(0x00FB & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x000D = C SET_REG1 A = 0x0D temp1.b = A ---------------- REG 0x000D = A SET_REG1 temp1 = 0x0D A = A + E ---------------- REG 0x000D = A REG 0x0005 = E ADD1 0x12 = 0x0D + 0x05 SET_REG1 A = 0x12 flag:c = temp1.b u> 0xff - E ---------------- REG 0x000D = temp1 REG 0x0005 = E SUB1 0xFA = 0xFF - 0x05 CMP_UGT 0 = 0x000D > 0x00FA SET_FLAG c = 0 C = A ---------------- REG 0x0012 = A SET_REG1 C = 0x12 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0005 = DE SUB2 0x0004 = 0x0005 - 0x0001 SET_REG2 DE = 0x0004 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 TEST_BIT 1 = bool(0x00FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 TEST_BIT 1 = bool(0x00FC & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0012 = C SET_REG1 A = 0x12 temp1.b = A ---------------- REG 0x0012 = A SET_REG1 temp1 = 0x12 A = A + E ---------------- REG 0x0012 = A REG 0x0004 = E ADD1 0x16 = 0x12 + 0x04 SET_REG1 A = 0x16 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0012 = temp1 REG 0x0004 = E SUB1 0xFB = 0xFF - 0x04 CMP_UGT 0 = 0x0012 > 0x00FB SET_FLAG c = 0 C = A ---------------- REG 0x0016 = A SET_REG1 C = 0x16 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0004 = DE SUB2 0x0003 = 0x0004 - 0x0001 SET_REG2 DE = 0x0003 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 TEST_BIT 1 = bool(0x00FD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 TEST_BIT 1 = bool(0x00FD & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0016 = C SET_REG1 A = 0x16 temp1.b = A ---------------- REG 0x0016 = A SET_REG1 temp1 = 0x16 A = A + E ---------------- REG 0x0016 = A REG 0x0003 = E ADD1 0x19 = 0x16 + 0x03 SET_REG1 A = 0x19 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0016 = temp1 REG 0x0003 = E SUB1 0xFC = 0xFF - 0x03 CMP_UGT 0 = 0x0016 > 0x00FC SET_FLAG c = 0 C = A ---------------- REG 0x0019 = A SET_REG1 C = 0x19 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0003 = DE SUB2 0x0002 = 0x0003 - 0x0001 SET_REG2 DE = 0x0002 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 TEST_BIT 1 = bool(0x00FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 TEST_BIT 1 = bool(0x00FE & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0019 = C SET_REG1 A = 0x19 temp1.b = A ---------------- REG 0x0019 = A SET_REG1 temp1 = 0x19 A = A + E ---------------- REG 0x0019 = A REG 0x0002 = E ADD1 0x1B = 0x19 + 0x02 SET_REG1 A = 0x1B flag:c = temp1.b u> 0xff - E ---------------- REG 0x0019 = temp1 REG 0x0002 = E SUB1 0xFD = 0xFF - 0x02 CMP_UGT 0 = 0x0019 > 0x00FD SET_FLAG c = 0 C = A ---------------- REG 0x001B = A SET_REG1 C = 0x1B A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0002 = DE SUB2 0x0001 = 0x0002 - 0x0001 SET_REG2 DE = 0x0001 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x001B = C SET_REG1 A = 0x1B temp1.b = A ---------------- REG 0x001B = A SET_REG1 temp1 = 0x1B A = A + E ---------------- REG 0x001B = A REG 0x0001 = E ADD1 0x1C = 0x1B + 0x01 SET_REG1 A = 0x1C flag:c = temp1.b u> 0xff - E ---------------- REG 0x001B = temp1 REG 0x0001 = E SUB1 0xFE = 0xFF - 0x01 CMP_UGT 0 = 0x001B > 0x00FE SET_FLAG c = 0 C = A ---------------- REG 0x001C = A SET_REG1 C = 0x1C A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0001 = DE SUB2 0x0000 = 0x0001 - 0x0001 SET_REG2 DE = 0x0000 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = E TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = E TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 0 = vm_flags[s] XOR 0x0001 = 0x0000 ^ 0x0001 L = C ---------------- REG 0x001C = C SET_REG1 L = 0x1C H = B ---------------- REG 0x0000 = B SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m triangle_down(7) (28 is correct) BC = 0 ---------------- SET_REG2 BC = 0x0000 HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE E = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0xA = mem[0x07FE] SET_REG1 E = 0x0A HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF D = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 D = 0x00 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x000A = E SUB1 0xF6 = 0x00 - 0x0A flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000A = E TEST_BIT 0 = bool(0x000A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000A = E TEST_BIT 0 = bool(0x000A & 0x0080) REG 0x0000 = A REG 0x000A = E SUB1 0xF6 = 0x00 - 0x0A TEST_BIT 1 = bool(0x00F6 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x000A = E SUB1 0xF6 = 0x00 - 0x0A TEST_BIT 1 = bool(0x00F6 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0000 = C SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = A + E ---------------- REG 0x0000 = A REG 0x000A = E ADD1 0x0A = 0x00 + 0x0A SET_REG1 A = 0x0A flag:c = temp1.b u> 0xff - E ---------------- REG 0x0000 = temp1 REG 0x000A = E SUB1 0xF5 = 0xFF - 0x0A CMP_UGT 0 = 0x0000 > 0x00F5 SET_FLAG c = 0 C = A ---------------- REG 0x000A = A SET_REG1 C = 0x0A A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x000A = DE SUB2 0x0009 = 0x000A - 0x0001 SET_REG2 DE = 0x0009 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0009 = E SUB1 0xF7 = 0x00 - 0x09 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0009 = E TEST_BIT 0 = bool(0x0009 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0009 = E TEST_BIT 0 = bool(0x0009 & 0x0080) REG 0x0000 = A REG 0x0009 = E SUB1 0xF7 = 0x00 - 0x09 TEST_BIT 1 = bool(0x00F7 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0009 = E SUB1 0xF7 = 0x00 - 0x09 TEST_BIT 1 = bool(0x00F7 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x000A = C SET_REG1 A = 0x0A temp1.b = A ---------------- REG 0x000A = A SET_REG1 temp1 = 0x0A A = A + E ---------------- REG 0x000A = A REG 0x0009 = E ADD1 0x13 = 0x0A + 0x09 SET_REG1 A = 0x13 flag:c = temp1.b u> 0xff - E ---------------- REG 0x000A = temp1 REG 0x0009 = E SUB1 0xF6 = 0xFF - 0x09 CMP_UGT 0 = 0x000A > 0x00F6 SET_FLAG c = 0 C = A ---------------- REG 0x0013 = A SET_REG1 C = 0x13 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0009 = DE SUB2 0x0008 = 0x0009 - 0x0001 SET_REG2 DE = 0x0008 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0008 = E SUB1 0xF8 = 0x00 - 0x08 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0008 = E TEST_BIT 0 = bool(0x0008 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0008 = E TEST_BIT 0 = bool(0x0008 & 0x0080) REG 0x0000 = A REG 0x0008 = E SUB1 0xF8 = 0x00 - 0x08 TEST_BIT 1 = bool(0x00F8 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0008 = E SUB1 0xF8 = 0x00 - 0x08 TEST_BIT 1 = bool(0x00F8 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0013 = C SET_REG1 A = 0x13 temp1.b = A ---------------- REG 0x0013 = A SET_REG1 temp1 = 0x13 A = A + E ---------------- REG 0x0013 = A REG 0x0008 = E ADD1 0x1B = 0x13 + 0x08 SET_REG1 A = 0x1B flag:c = temp1.b u> 0xff - E ---------------- REG 0x0013 = temp1 REG 0x0008 = E SUB1 0xF7 = 0xFF - 0x08 CMP_UGT 0 = 0x0013 > 0x00F7 SET_FLAG c = 0 C = A ---------------- REG 0x001B = A SET_REG1 C = 0x1B A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0008 = DE SUB2 0x0007 = 0x0008 - 0x0001 SET_REG2 DE = 0x0007 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0007 = E SUB1 0xF9 = 0x00 - 0x07 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x0000 = A REG 0x0007 = E SUB1 0xF9 = 0x00 - 0x07 TEST_BIT 1 = bool(0x00F9 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0007 = E SUB1 0xF9 = 0x00 - 0x07 TEST_BIT 1 = bool(0x00F9 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x001B = C SET_REG1 A = 0x1B temp1.b = A ---------------- REG 0x001B = A SET_REG1 temp1 = 0x1B A = A + E ---------------- REG 0x001B = A REG 0x0007 = E ADD1 0x22 = 0x1B + 0x07 SET_REG1 A = 0x22 flag:c = temp1.b u> 0xff - E ---------------- REG 0x001B = temp1 REG 0x0007 = E SUB1 0xF8 = 0xFF - 0x07 CMP_UGT 0 = 0x001B > 0x00F8 SET_FLAG c = 0 C = A ---------------- REG 0x0022 = A SET_REG1 C = 0x22 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0007 = DE SUB2 0x0006 = 0x0007 - 0x0001 SET_REG2 DE = 0x0006 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0006 = E SUB1 0xFA = 0x00 - 0x06 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) REG 0x0000 = A REG 0x0006 = E SUB1 0xFA = 0x00 - 0x06 TEST_BIT 1 = bool(0x00FA & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0006 = E SUB1 0xFA = 0x00 - 0x06 TEST_BIT 1 = bool(0x00FA & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0022 = C SET_REG1 A = 0x22 temp1.b = A ---------------- REG 0x0022 = A SET_REG1 temp1 = 0x22 A = A + E ---------------- REG 0x0022 = A REG 0x0006 = E ADD1 0x28 = 0x22 + 0x06 SET_REG1 A = 0x28 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0022 = temp1 REG 0x0006 = E SUB1 0xF9 = 0xFF - 0x06 CMP_UGT 0 = 0x0022 > 0x00F9 SET_FLAG c = 0 C = A ---------------- REG 0x0028 = A SET_REG1 C = 0x28 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0006 = DE SUB2 0x0005 = 0x0006 - 0x0001 SET_REG2 DE = 0x0005 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0005 = E SUB1 0xFB = 0x00 - 0x05 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) REG 0x0000 = A REG 0x0005 = E SUB1 0xFB = 0x00 - 0x05 TEST_BIT 1 = bool(0x00FB & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0005 = E SUB1 0xFB = 0x00 - 0x05 TEST_BIT 1 = bool(0x00FB & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0028 = C SET_REG1 A = 0x28 temp1.b = A ---------------- REG 0x0028 = A SET_REG1 temp1 = 0x28 A = A + E ---------------- REG 0x0028 = A REG 0x0005 = E ADD1 0x2D = 0x28 + 0x05 SET_REG1 A = 0x2D flag:c = temp1.b u> 0xff - E ---------------- REG 0x0028 = temp1 REG 0x0005 = E SUB1 0xFA = 0xFF - 0x05 CMP_UGT 0 = 0x0028 > 0x00FA SET_FLAG c = 0 C = A ---------------- REG 0x002D = A SET_REG1 C = 0x2D A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0005 = DE SUB2 0x0004 = 0x0005 - 0x0001 SET_REG2 DE = 0x0004 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 TEST_BIT 1 = bool(0x00FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 TEST_BIT 1 = bool(0x00FC & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x002D = C SET_REG1 A = 0x2D temp1.b = A ---------------- REG 0x002D = A SET_REG1 temp1 = 0x2D A = A + E ---------------- REG 0x002D = A REG 0x0004 = E ADD1 0x31 = 0x2D + 0x04 SET_REG1 A = 0x31 flag:c = temp1.b u> 0xff - E ---------------- REG 0x002D = temp1 REG 0x0004 = E SUB1 0xFB = 0xFF - 0x04 CMP_UGT 0 = 0x002D > 0x00FB SET_FLAG c = 0 C = A ---------------- REG 0x0031 = A SET_REG1 C = 0x31 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0004 = DE SUB2 0x0003 = 0x0004 - 0x0001 SET_REG2 DE = 0x0003 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 TEST_BIT 1 = bool(0x00FD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 TEST_BIT 1 = bool(0x00FD & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0031 = C SET_REG1 A = 0x31 temp1.b = A ---------------- REG 0x0031 = A SET_REG1 temp1 = 0x31 A = A + E ---------------- REG 0x0031 = A REG 0x0003 = E ADD1 0x34 = 0x31 + 0x03 SET_REG1 A = 0x34 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0031 = temp1 REG 0x0003 = E SUB1 0xFC = 0xFF - 0x03 CMP_UGT 0 = 0x0031 > 0x00FC SET_FLAG c = 0 C = A ---------------- REG 0x0034 = A SET_REG1 C = 0x34 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0003 = DE SUB2 0x0002 = 0x0003 - 0x0001 SET_REG2 DE = 0x0002 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 TEST_BIT 1 = bool(0x00FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 TEST_BIT 1 = bool(0x00FE & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0034 = C SET_REG1 A = 0x34 temp1.b = A ---------------- REG 0x0034 = A SET_REG1 temp1 = 0x34 A = A + E ---------------- REG 0x0034 = A REG 0x0002 = E ADD1 0x36 = 0x34 + 0x02 SET_REG1 A = 0x36 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0034 = temp1 REG 0x0002 = E SUB1 0xFD = 0xFF - 0x02 CMP_UGT 0 = 0x0034 > 0x00FD SET_FLAG c = 0 C = A ---------------- REG 0x0036 = A SET_REG1 C = 0x36 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0002 = DE SUB2 0x0001 = 0x0002 - 0x0001 SET_REG2 DE = 0x0001 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0036 = C SET_REG1 A = 0x36 temp1.b = A ---------------- REG 0x0036 = A SET_REG1 temp1 = 0x36 A = A + E ---------------- REG 0x0036 = A REG 0x0001 = E ADD1 0x37 = 0x36 + 0x01 SET_REG1 A = 0x37 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0036 = temp1 REG 0x0001 = E SUB1 0xFE = 0xFF - 0x01 CMP_UGT 0 = 0x0036 > 0x00FE SET_FLAG c = 0 C = A ---------------- REG 0x0037 = A SET_REG1 C = 0x37 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0001 = DE SUB2 0x0000 = 0x0001 - 0x0001 SET_REG2 DE = 0x0000 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = E TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = E TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 0 = vm_flags[s] XOR 0x0001 = 0x0000 ^ 0x0001 L = C ---------------- REG 0x0037 = C SET_REG1 L = 0x37 H = B ---------------- REG 0x0000 = B SET_REG1 H = 0x00 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m triangle_down(10) (55 is correct) BC = 0 ---------------- SET_REG2 BC = 0x0000 HL = 2 ---------------- SET_REG2 HL = 0x0002 HL = HL + SP {arg1} ---------------- REG 0x0002 = HL REG 0x07FC = SP ADD2 0x07FE = 0x0002 + 0x07FC SET_REG2 HL = 0x07FE E = [HL {arg1}].b ---------------- REG 0x07FE = HL LOAD1 0x64 = mem[0x07FE] SET_REG1 E = 0x64 HL = HL + 1 {arg2} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF D = [HL {arg2}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 D = 0x00 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0064 = E SUB1 0x9C = 0x00 - 0x64 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0064 = E TEST_BIT 0 = bool(0x0064 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0064 = E TEST_BIT 0 = bool(0x0064 & 0x0080) REG 0x0000 = A REG 0x0064 = E SUB1 0x9C = 0x00 - 0x64 TEST_BIT 1 = bool(0x009C & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0064 = E SUB1 0x9C = 0x00 - 0x64 TEST_BIT 1 = bool(0x009C & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0000 = C SET_REG1 A = 0x00 temp1.b = A ---------------- REG 0x0000 = A SET_REG1 temp1 = 0x00 A = A + E ---------------- REG 0x0000 = A REG 0x0064 = E ADD1 0x64 = 0x00 + 0x64 SET_REG1 A = 0x64 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0000 = temp1 REG 0x0064 = E SUB1 0x9B = 0xFF - 0x64 CMP_UGT 0 = 0x0000 > 0x009B SET_FLAG c = 0 C = A ---------------- REG 0x0064 = A SET_REG1 C = 0x64 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0064 = DE SUB2 0x0063 = 0x0064 - 0x0001 SET_REG2 DE = 0x0063 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0063 = E SUB1 0x9D = 0x00 - 0x63 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0063 = E TEST_BIT 0 = bool(0x0063 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0063 = E TEST_BIT 0 = bool(0x0063 & 0x0080) REG 0x0000 = A REG 0x0063 = E SUB1 0x9D = 0x00 - 0x63 TEST_BIT 1 = bool(0x009D & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0063 = E SUB1 0x9D = 0x00 - 0x63 TEST_BIT 1 = bool(0x009D & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0064 = C SET_REG1 A = 0x64 temp1.b = A ---------------- REG 0x0064 = A SET_REG1 temp1 = 0x64 A = A + E ---------------- REG 0x0064 = A REG 0x0063 = E ADD1 0xC7 = 0x64 + 0x63 SET_REG1 A = 0xC7 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0064 = temp1 REG 0x0063 = E SUB1 0x9C = 0xFF - 0x63 CMP_UGT 0 = 0x0064 > 0x009C SET_FLAG c = 0 C = A ---------------- REG 0x00C7 = A SET_REG1 C = 0xC7 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0000 = 0x0000 + 0x0000 + 0 SET_REG1 A = 0x00 B = A ---------------- REG 0x0000 = A SET_REG1 B = 0x00 DE = DE - 1 ---------------- REG 0x0063 = DE SUB2 0x0062 = 0x0063 - 0x0001 SET_REG2 DE = 0x0062 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0062 = E SUB1 0x9E = 0x00 - 0x62 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0062 = E TEST_BIT 0 = bool(0x0062 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0062 = E TEST_BIT 0 = bool(0x0062 & 0x0080) REG 0x0000 = A REG 0x0062 = E SUB1 0x9E = 0x00 - 0x62 TEST_BIT 1 = bool(0x009E & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0062 = E SUB1 0x9E = 0x00 - 0x62 TEST_BIT 1 = bool(0x009E & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00C7 = C SET_REG1 A = 0xC7 temp1.b = A ---------------- REG 0x00C7 = A SET_REG1 temp1 = 0xC7 A = A + E ---------------- REG 0x00C7 = A REG 0x0062 = E ADD1 0x29 = 0xC7 + 0x62 SET_REG1 A = 0x29 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00C7 = temp1 REG 0x0062 = E SUB1 0x9D = 0xFF - 0x62 CMP_UGT 1 = 0x00C7 > 0x009D SET_FLAG c = 1 C = A ---------------- REG 0x0029 = A SET_REG1 C = 0x29 A = B ---------------- REG 0x0000 = B SET_REG1 A = 0x00 A = adc.b(A, D, flag:c) ---------------- REG 0x0000 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0001 = 0x0000 + 0x0000 + 1 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE - 1 ---------------- REG 0x0062 = DE SUB2 0x0061 = 0x0062 - 0x0001 SET_REG2 DE = 0x0061 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0061 = E SUB1 0x9F = 0x00 - 0x61 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0061 = E TEST_BIT 0 = bool(0x0061 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0061 = E TEST_BIT 0 = bool(0x0061 & 0x0080) REG 0x0000 = A REG 0x0061 = E SUB1 0x9F = 0x00 - 0x61 TEST_BIT 1 = bool(0x009F & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0061 = E SUB1 0x9F = 0x00 - 0x61 TEST_BIT 1 = bool(0x009F & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0029 = C SET_REG1 A = 0x29 temp1.b = A ---------------- REG 0x0029 = A SET_REG1 temp1 = 0x29 A = A + E ---------------- REG 0x0029 = A REG 0x0061 = E ADD1 0x8A = 0x29 + 0x61 SET_REG1 A = 0x8A flag:c = temp1.b u> 0xff - E ---------------- REG 0x0029 = temp1 REG 0x0061 = E SUB1 0x9E = 0xFF - 0x61 CMP_UGT 0 = 0x0029 > 0x009E SET_FLAG c = 0 C = A ---------------- REG 0x008A = A SET_REG1 C = 0x8A A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0001 = 0x0001 + 0x0000 + 0 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE - 1 ---------------- REG 0x0061 = DE SUB2 0x0060 = 0x0061 - 0x0001 SET_REG2 DE = 0x0060 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0060 = E SUB1 0xA0 = 0x00 - 0x60 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0060 = E TEST_BIT 0 = bool(0x0060 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0060 = E TEST_BIT 0 = bool(0x0060 & 0x0080) REG 0x0000 = A REG 0x0060 = E SUB1 0xA0 = 0x00 - 0x60 TEST_BIT 1 = bool(0x00A0 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0060 = E SUB1 0xA0 = 0x00 - 0x60 TEST_BIT 1 = bool(0x00A0 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x008A = C SET_REG1 A = 0x8A temp1.b = A ---------------- REG 0x008A = A SET_REG1 temp1 = 0x8A A = A + E ---------------- REG 0x008A = A REG 0x0060 = E ADD1 0xEA = 0x8A + 0x60 SET_REG1 A = 0xEA flag:c = temp1.b u> 0xff - E ---------------- REG 0x008A = temp1 REG 0x0060 = E SUB1 0x9F = 0xFF - 0x60 CMP_UGT 0 = 0x008A > 0x009F SET_FLAG c = 0 C = A ---------------- REG 0x00EA = A SET_REG1 C = 0xEA A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0001 = 0x0001 + 0x0000 + 0 SET_REG1 A = 0x01 B = A ---------------- REG 0x0001 = A SET_REG1 B = 0x01 DE = DE - 1 ---------------- REG 0x0060 = DE SUB2 0x005F = 0x0060 - 0x0001 SET_REG2 DE = 0x005F goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x005F = E SUB1 0xA1 = 0x00 - 0x5F flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005F = E TEST_BIT 0 = bool(0x005F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005F = E TEST_BIT 0 = bool(0x005F & 0x0080) REG 0x0000 = A REG 0x005F = E SUB1 0xA1 = 0x00 - 0x5F TEST_BIT 1 = bool(0x00A1 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x005F = E SUB1 0xA1 = 0x00 - 0x5F TEST_BIT 1 = bool(0x00A1 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00EA = C SET_REG1 A = 0xEA temp1.b = A ---------------- REG 0x00EA = A SET_REG1 temp1 = 0xEA A = A + E ---------------- REG 0x00EA = A REG 0x005F = E ADD1 0x49 = 0xEA + 0x5F SET_REG1 A = 0x49 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00EA = temp1 REG 0x005F = E SUB1 0xA0 = 0xFF - 0x5F CMP_UGT 1 = 0x00EA > 0x00A0 SET_FLAG c = 1 C = A ---------------- REG 0x0049 = A SET_REG1 C = 0x49 A = B ---------------- REG 0x0001 = B SET_REG1 A = 0x01 A = adc.b(A, D, flag:c) ---------------- REG 0x0001 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0002 = 0x0001 + 0x0000 + 1 SET_REG1 A = 0x02 B = A ---------------- REG 0x0002 = A SET_REG1 B = 0x02 DE = DE - 1 ---------------- REG 0x005F = DE SUB2 0x005E = 0x005F - 0x0001 SET_REG2 DE = 0x005E goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x005E = E SUB1 0xA2 = 0x00 - 0x5E flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005E = E TEST_BIT 0 = bool(0x005E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005E = E TEST_BIT 0 = bool(0x005E & 0x0080) REG 0x0000 = A REG 0x005E = E SUB1 0xA2 = 0x00 - 0x5E TEST_BIT 1 = bool(0x00A2 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x005E = E SUB1 0xA2 = 0x00 - 0x5E TEST_BIT 1 = bool(0x00A2 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0049 = C SET_REG1 A = 0x49 temp1.b = A ---------------- REG 0x0049 = A SET_REG1 temp1 = 0x49 A = A + E ---------------- REG 0x0049 = A REG 0x005E = E ADD1 0xA7 = 0x49 + 0x5E SET_REG1 A = 0xA7 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0049 = temp1 REG 0x005E = E SUB1 0xA1 = 0xFF - 0x5E CMP_UGT 0 = 0x0049 > 0x00A1 SET_FLAG c = 0 C = A ---------------- REG 0x00A7 = A SET_REG1 C = 0xA7 A = B ---------------- REG 0x0002 = B SET_REG1 A = 0x02 A = adc.b(A, D, flag:c) ---------------- REG 0x0002 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0002 = 0x0002 + 0x0000 + 0 SET_REG1 A = 0x02 B = A ---------------- REG 0x0002 = A SET_REG1 B = 0x02 DE = DE - 1 ---------------- REG 0x005E = DE SUB2 0x005D = 0x005E - 0x0001 SET_REG2 DE = 0x005D goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x005D = E SUB1 0xA3 = 0x00 - 0x5D flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005D = E TEST_BIT 0 = bool(0x005D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005D = E TEST_BIT 0 = bool(0x005D & 0x0080) REG 0x0000 = A REG 0x005D = E SUB1 0xA3 = 0x00 - 0x5D TEST_BIT 1 = bool(0x00A3 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x005D = E SUB1 0xA3 = 0x00 - 0x5D TEST_BIT 1 = bool(0x00A3 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00A7 = C SET_REG1 A = 0xA7 temp1.b = A ---------------- REG 0x00A7 = A SET_REG1 temp1 = 0xA7 A = A + E ---------------- REG 0x00A7 = A REG 0x005D = E ADD1 0x04 = 0xA7 + 0x5D SET_REG1 A = 0x04 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00A7 = temp1 REG 0x005D = E SUB1 0xA2 = 0xFF - 0x5D CMP_UGT 1 = 0x00A7 > 0x00A2 SET_FLAG c = 1 C = A ---------------- REG 0x0004 = A SET_REG1 C = 0x04 A = B ---------------- REG 0x0002 = B SET_REG1 A = 0x02 A = adc.b(A, D, flag:c) ---------------- REG 0x0002 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0003 = 0x0002 + 0x0000 + 1 SET_REG1 A = 0x03 B = A ---------------- REG 0x0003 = A SET_REG1 B = 0x03 DE = DE - 1 ---------------- REG 0x005D = DE SUB2 0x005C = 0x005D - 0x0001 SET_REG2 DE = 0x005C goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x005C = E SUB1 0xA4 = 0x00 - 0x5C flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005C = E TEST_BIT 0 = bool(0x005C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005C = E TEST_BIT 0 = bool(0x005C & 0x0080) REG 0x0000 = A REG 0x005C = E SUB1 0xA4 = 0x00 - 0x5C TEST_BIT 1 = bool(0x00A4 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x005C = E SUB1 0xA4 = 0x00 - 0x5C TEST_BIT 1 = bool(0x00A4 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0004 = C SET_REG1 A = 0x04 temp1.b = A ---------------- REG 0x0004 = A SET_REG1 temp1 = 0x04 A = A + E ---------------- REG 0x0004 = A REG 0x005C = E ADD1 0x60 = 0x04 + 0x5C SET_REG1 A = 0x60 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0004 = temp1 REG 0x005C = E SUB1 0xA3 = 0xFF - 0x5C CMP_UGT 0 = 0x0004 > 0x00A3 SET_FLAG c = 0 C = A ---------------- REG 0x0060 = A SET_REG1 C = 0x60 A = B ---------------- REG 0x0003 = B SET_REG1 A = 0x03 A = adc.b(A, D, flag:c) ---------------- REG 0x0003 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0003 = 0x0003 + 0x0000 + 0 SET_REG1 A = 0x03 B = A ---------------- REG 0x0003 = A SET_REG1 B = 0x03 DE = DE - 1 ---------------- REG 0x005C = DE SUB2 0x005B = 0x005C - 0x0001 SET_REG2 DE = 0x005B goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x005B = E SUB1 0xA5 = 0x00 - 0x5B flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005B = E TEST_BIT 0 = bool(0x005B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005B = E TEST_BIT 0 = bool(0x005B & 0x0080) REG 0x0000 = A REG 0x005B = E SUB1 0xA5 = 0x00 - 0x5B TEST_BIT 1 = bool(0x00A5 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x005B = E SUB1 0xA5 = 0x00 - 0x5B TEST_BIT 1 = bool(0x00A5 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0060 = C SET_REG1 A = 0x60 temp1.b = A ---------------- REG 0x0060 = A SET_REG1 temp1 = 0x60 A = A + E ---------------- REG 0x0060 = A REG 0x005B = E ADD1 0xBB = 0x60 + 0x5B SET_REG1 A = 0xBB flag:c = temp1.b u> 0xff - E ---------------- REG 0x0060 = temp1 REG 0x005B = E SUB1 0xA4 = 0xFF - 0x5B CMP_UGT 0 = 0x0060 > 0x00A4 SET_FLAG c = 0 C = A ---------------- REG 0x00BB = A SET_REG1 C = 0xBB A = B ---------------- REG 0x0003 = B SET_REG1 A = 0x03 A = adc.b(A, D, flag:c) ---------------- REG 0x0003 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0003 = 0x0003 + 0x0000 + 0 SET_REG1 A = 0x03 B = A ---------------- REG 0x0003 = A SET_REG1 B = 0x03 DE = DE - 1 ---------------- REG 0x005B = DE SUB2 0x005A = 0x005B - 0x0001 SET_REG2 DE = 0x005A goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x005A = E SUB1 0xA6 = 0x00 - 0x5A flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x005A = E TEST_BIT 0 = bool(0x005A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x005A = E TEST_BIT 0 = bool(0x005A & 0x0080) REG 0x0000 = A REG 0x005A = E SUB1 0xA6 = 0x00 - 0x5A TEST_BIT 1 = bool(0x00A6 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x005A = E SUB1 0xA6 = 0x00 - 0x5A TEST_BIT 1 = bool(0x00A6 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00BB = C SET_REG1 A = 0xBB temp1.b = A ---------------- REG 0x00BB = A SET_REG1 temp1 = 0xBB A = A + E ---------------- REG 0x00BB = A REG 0x005A = E ADD1 0x15 = 0xBB + 0x5A SET_REG1 A = 0x15 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00BB = temp1 REG 0x005A = E SUB1 0xA5 = 0xFF - 0x5A CMP_UGT 1 = 0x00BB > 0x00A5 SET_FLAG c = 1 C = A ---------------- REG 0x0015 = A SET_REG1 C = 0x15 A = B ---------------- REG 0x0003 = B SET_REG1 A = 0x03 A = adc.b(A, D, flag:c) ---------------- REG 0x0003 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0004 = 0x0003 + 0x0000 + 1 SET_REG1 A = 0x04 B = A ---------------- REG 0x0004 = A SET_REG1 B = 0x04 DE = DE - 1 ---------------- REG 0x005A = DE SUB2 0x0059 = 0x005A - 0x0001 SET_REG2 DE = 0x0059 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0059 = E SUB1 0xA7 = 0x00 - 0x59 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0059 = E TEST_BIT 0 = bool(0x0059 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0059 = E TEST_BIT 0 = bool(0x0059 & 0x0080) REG 0x0000 = A REG 0x0059 = E SUB1 0xA7 = 0x00 - 0x59 TEST_BIT 1 = bool(0x00A7 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0059 = E SUB1 0xA7 = 0x00 - 0x59 TEST_BIT 1 = bool(0x00A7 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0015 = C SET_REG1 A = 0x15 temp1.b = A ---------------- REG 0x0015 = A SET_REG1 temp1 = 0x15 A = A + E ---------------- REG 0x0015 = A REG 0x0059 = E ADD1 0x6E = 0x15 + 0x59 SET_REG1 A = 0x6E flag:c = temp1.b u> 0xff - E ---------------- REG 0x0015 = temp1 REG 0x0059 = E SUB1 0xA6 = 0xFF - 0x59 CMP_UGT 0 = 0x0015 > 0x00A6 SET_FLAG c = 0 C = A ---------------- REG 0x006E = A SET_REG1 C = 0x6E A = B ---------------- REG 0x0004 = B SET_REG1 A = 0x04 A = adc.b(A, D, flag:c) ---------------- REG 0x0004 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0004 = 0x0004 + 0x0000 + 0 SET_REG1 A = 0x04 B = A ---------------- REG 0x0004 = A SET_REG1 B = 0x04 DE = DE - 1 ---------------- REG 0x0059 = DE SUB2 0x0058 = 0x0059 - 0x0001 SET_REG2 DE = 0x0058 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0058 = E SUB1 0xA8 = 0x00 - 0x58 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0058 = E TEST_BIT 0 = bool(0x0058 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0058 = E TEST_BIT 0 = bool(0x0058 & 0x0080) REG 0x0000 = A REG 0x0058 = E SUB1 0xA8 = 0x00 - 0x58 TEST_BIT 1 = bool(0x00A8 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0058 = E SUB1 0xA8 = 0x00 - 0x58 TEST_BIT 1 = bool(0x00A8 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x006E = C SET_REG1 A = 0x6E temp1.b = A ---------------- REG 0x006E = A SET_REG1 temp1 = 0x6E A = A + E ---------------- REG 0x006E = A REG 0x0058 = E ADD1 0xC6 = 0x6E + 0x58 SET_REG1 A = 0xC6 flag:c = temp1.b u> 0xff - E ---------------- REG 0x006E = temp1 REG 0x0058 = E SUB1 0xA7 = 0xFF - 0x58 CMP_UGT 0 = 0x006E > 0x00A7 SET_FLAG c = 0 C = A ---------------- REG 0x00C6 = A SET_REG1 C = 0xC6 A = B ---------------- REG 0x0004 = B SET_REG1 A = 0x04 A = adc.b(A, D, flag:c) ---------------- REG 0x0004 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0004 = 0x0004 + 0x0000 + 0 SET_REG1 A = 0x04 B = A ---------------- REG 0x0004 = A SET_REG1 B = 0x04 DE = DE - 1 ---------------- REG 0x0058 = DE SUB2 0x0057 = 0x0058 - 0x0001 SET_REG2 DE = 0x0057 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0057 = E SUB1 0xA9 = 0x00 - 0x57 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0057 = E TEST_BIT 0 = bool(0x0057 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0057 = E TEST_BIT 0 = bool(0x0057 & 0x0080) REG 0x0000 = A REG 0x0057 = E SUB1 0xA9 = 0x00 - 0x57 TEST_BIT 1 = bool(0x00A9 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0057 = E SUB1 0xA9 = 0x00 - 0x57 TEST_BIT 1 = bool(0x00A9 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00C6 = C SET_REG1 A = 0xC6 temp1.b = A ---------------- REG 0x00C6 = A SET_REG1 temp1 = 0xC6 A = A + E ---------------- REG 0x00C6 = A REG 0x0057 = E ADD1 0x1D = 0xC6 + 0x57 SET_REG1 A = 0x1D flag:c = temp1.b u> 0xff - E ---------------- REG 0x00C6 = temp1 REG 0x0057 = E SUB1 0xA8 = 0xFF - 0x57 CMP_UGT 1 = 0x00C6 > 0x00A8 SET_FLAG c = 1 C = A ---------------- REG 0x001D = A SET_REG1 C = 0x1D A = B ---------------- REG 0x0004 = B SET_REG1 A = 0x04 A = adc.b(A, D, flag:c) ---------------- REG 0x0004 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0005 = 0x0004 + 0x0000 + 1 SET_REG1 A = 0x05 B = A ---------------- REG 0x0005 = A SET_REG1 B = 0x05 DE = DE - 1 ---------------- REG 0x0057 = DE SUB2 0x0056 = 0x0057 - 0x0001 SET_REG2 DE = 0x0056 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0056 = E SUB1 0xAA = 0x00 - 0x56 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0056 = E TEST_BIT 0 = bool(0x0056 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0056 = E TEST_BIT 0 = bool(0x0056 & 0x0080) REG 0x0000 = A REG 0x0056 = E SUB1 0xAA = 0x00 - 0x56 TEST_BIT 1 = bool(0x00AA & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0056 = E SUB1 0xAA = 0x00 - 0x56 TEST_BIT 1 = bool(0x00AA & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x001D = C SET_REG1 A = 0x1D temp1.b = A ---------------- REG 0x001D = A SET_REG1 temp1 = 0x1D A = A + E ---------------- REG 0x001D = A REG 0x0056 = E ADD1 0x73 = 0x1D + 0x56 SET_REG1 A = 0x73 flag:c = temp1.b u> 0xff - E ---------------- REG 0x001D = temp1 REG 0x0056 = E SUB1 0xA9 = 0xFF - 0x56 CMP_UGT 0 = 0x001D > 0x00A9 SET_FLAG c = 0 C = A ---------------- REG 0x0073 = A SET_REG1 C = 0x73 A = B ---------------- REG 0x0005 = B SET_REG1 A = 0x05 A = adc.b(A, D, flag:c) ---------------- REG 0x0005 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0005 = 0x0005 + 0x0000 + 0 SET_REG1 A = 0x05 B = A ---------------- REG 0x0005 = A SET_REG1 B = 0x05 DE = DE - 1 ---------------- REG 0x0056 = DE SUB2 0x0055 = 0x0056 - 0x0001 SET_REG2 DE = 0x0055 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0055 = E SUB1 0xAB = 0x00 - 0x55 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0055 = E TEST_BIT 0 = bool(0x0055 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0055 = E TEST_BIT 0 = bool(0x0055 & 0x0080) REG 0x0000 = A REG 0x0055 = E SUB1 0xAB = 0x00 - 0x55 TEST_BIT 1 = bool(0x00AB & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0055 = E SUB1 0xAB = 0x00 - 0x55 TEST_BIT 1 = bool(0x00AB & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0073 = C SET_REG1 A = 0x73 temp1.b = A ---------------- REG 0x0073 = A SET_REG1 temp1 = 0x73 A = A + E ---------------- REG 0x0073 = A REG 0x0055 = E ADD1 0xC8 = 0x73 + 0x55 SET_REG1 A = 0xC8 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0073 = temp1 REG 0x0055 = E SUB1 0xAA = 0xFF - 0x55 CMP_UGT 0 = 0x0073 > 0x00AA SET_FLAG c = 0 C = A ---------------- REG 0x00C8 = A SET_REG1 C = 0xC8 A = B ---------------- REG 0x0005 = B SET_REG1 A = 0x05 A = adc.b(A, D, flag:c) ---------------- REG 0x0005 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0005 = 0x0005 + 0x0000 + 0 SET_REG1 A = 0x05 B = A ---------------- REG 0x0005 = A SET_REG1 B = 0x05 DE = DE - 1 ---------------- REG 0x0055 = DE SUB2 0x0054 = 0x0055 - 0x0001 SET_REG2 DE = 0x0054 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0054 = E SUB1 0xAC = 0x00 - 0x54 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0054 = E TEST_BIT 0 = bool(0x0054 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0054 = E TEST_BIT 0 = bool(0x0054 & 0x0080) REG 0x0000 = A REG 0x0054 = E SUB1 0xAC = 0x00 - 0x54 TEST_BIT 1 = bool(0x00AC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0054 = E SUB1 0xAC = 0x00 - 0x54 TEST_BIT 1 = bool(0x00AC & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00C8 = C SET_REG1 A = 0xC8 temp1.b = A ---------------- REG 0x00C8 = A SET_REG1 temp1 = 0xC8 A = A + E ---------------- REG 0x00C8 = A REG 0x0054 = E ADD1 0x1C = 0xC8 + 0x54 SET_REG1 A = 0x1C flag:c = temp1.b u> 0xff - E ---------------- REG 0x00C8 = temp1 REG 0x0054 = E SUB1 0xAB = 0xFF - 0x54 CMP_UGT 1 = 0x00C8 > 0x00AB SET_FLAG c = 1 C = A ---------------- REG 0x001C = A SET_REG1 C = 0x1C A = B ---------------- REG 0x0005 = B SET_REG1 A = 0x05 A = adc.b(A, D, flag:c) ---------------- REG 0x0005 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0006 = 0x0005 + 0x0000 + 1 SET_REG1 A = 0x06 B = A ---------------- REG 0x0006 = A SET_REG1 B = 0x06 DE = DE - 1 ---------------- REG 0x0054 = DE SUB2 0x0053 = 0x0054 - 0x0001 SET_REG2 DE = 0x0053 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0053 = E SUB1 0xAD = 0x00 - 0x53 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0053 = E TEST_BIT 0 = bool(0x0053 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0053 = E TEST_BIT 0 = bool(0x0053 & 0x0080) REG 0x0000 = A REG 0x0053 = E SUB1 0xAD = 0x00 - 0x53 TEST_BIT 1 = bool(0x00AD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0053 = E SUB1 0xAD = 0x00 - 0x53 TEST_BIT 1 = bool(0x00AD & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x001C = C SET_REG1 A = 0x1C temp1.b = A ---------------- REG 0x001C = A SET_REG1 temp1 = 0x1C A = A + E ---------------- REG 0x001C = A REG 0x0053 = E ADD1 0x6F = 0x1C + 0x53 SET_REG1 A = 0x6F flag:c = temp1.b u> 0xff - E ---------------- REG 0x001C = temp1 REG 0x0053 = E SUB1 0xAC = 0xFF - 0x53 CMP_UGT 0 = 0x001C > 0x00AC SET_FLAG c = 0 C = A ---------------- REG 0x006F = A SET_REG1 C = 0x6F A = B ---------------- REG 0x0006 = B SET_REG1 A = 0x06 A = adc.b(A, D, flag:c) ---------------- REG 0x0006 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0006 = 0x0006 + 0x0000 + 0 SET_REG1 A = 0x06 B = A ---------------- REG 0x0006 = A SET_REG1 B = 0x06 DE = DE - 1 ---------------- REG 0x0053 = DE SUB2 0x0052 = 0x0053 - 0x0001 SET_REG2 DE = 0x0052 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0052 = E SUB1 0xAE = 0x00 - 0x52 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0052 = E TEST_BIT 0 = bool(0x0052 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0052 = E TEST_BIT 0 = bool(0x0052 & 0x0080) REG 0x0000 = A REG 0x0052 = E SUB1 0xAE = 0x00 - 0x52 TEST_BIT 1 = bool(0x00AE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0052 = E SUB1 0xAE = 0x00 - 0x52 TEST_BIT 1 = bool(0x00AE & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x006F = C SET_REG1 A = 0x6F temp1.b = A ---------------- REG 0x006F = A SET_REG1 temp1 = 0x6F A = A + E ---------------- REG 0x006F = A REG 0x0052 = E ADD1 0xC1 = 0x6F + 0x52 SET_REG1 A = 0xC1 flag:c = temp1.b u> 0xff - E ---------------- REG 0x006F = temp1 REG 0x0052 = E SUB1 0xAD = 0xFF - 0x52 CMP_UGT 0 = 0x006F > 0x00AD SET_FLAG c = 0 C = A ---------------- REG 0x00C1 = A SET_REG1 C = 0xC1 A = B ---------------- REG 0x0006 = B SET_REG1 A = 0x06 A = adc.b(A, D, flag:c) ---------------- REG 0x0006 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0006 = 0x0006 + 0x0000 + 0 SET_REG1 A = 0x06 B = A ---------------- REG 0x0006 = A SET_REG1 B = 0x06 DE = DE - 1 ---------------- REG 0x0052 = DE SUB2 0x0051 = 0x0052 - 0x0001 SET_REG2 DE = 0x0051 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0051 = E SUB1 0xAF = 0x00 - 0x51 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0051 = E TEST_BIT 0 = bool(0x0051 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0051 = E TEST_BIT 0 = bool(0x0051 & 0x0080) REG 0x0000 = A REG 0x0051 = E SUB1 0xAF = 0x00 - 0x51 TEST_BIT 1 = bool(0x00AF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0051 = E SUB1 0xAF = 0x00 - 0x51 TEST_BIT 1 = bool(0x00AF & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00C1 = C SET_REG1 A = 0xC1 temp1.b = A ---------------- REG 0x00C1 = A SET_REG1 temp1 = 0xC1 A = A + E ---------------- REG 0x00C1 = A REG 0x0051 = E ADD1 0x12 = 0xC1 + 0x51 SET_REG1 A = 0x12 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00C1 = temp1 REG 0x0051 = E SUB1 0xAE = 0xFF - 0x51 CMP_UGT 1 = 0x00C1 > 0x00AE SET_FLAG c = 1 C = A ---------------- REG 0x0012 = A SET_REG1 C = 0x12 A = B ---------------- REG 0x0006 = B SET_REG1 A = 0x06 A = adc.b(A, D, flag:c) ---------------- REG 0x0006 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0007 = 0x0006 + 0x0000 + 1 SET_REG1 A = 0x07 B = A ---------------- REG 0x0007 = A SET_REG1 B = 0x07 DE = DE - 1 ---------------- REG 0x0051 = DE SUB2 0x0050 = 0x0051 - 0x0001 SET_REG2 DE = 0x0050 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0050 = E SUB1 0xB0 = 0x00 - 0x50 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0050 = E TEST_BIT 0 = bool(0x0050 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0050 = E TEST_BIT 0 = bool(0x0050 & 0x0080) REG 0x0000 = A REG 0x0050 = E SUB1 0xB0 = 0x00 - 0x50 TEST_BIT 1 = bool(0x00B0 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0050 = E SUB1 0xB0 = 0x00 - 0x50 TEST_BIT 1 = bool(0x00B0 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0012 = C SET_REG1 A = 0x12 temp1.b = A ---------------- REG 0x0012 = A SET_REG1 temp1 = 0x12 A = A + E ---------------- REG 0x0012 = A REG 0x0050 = E ADD1 0x62 = 0x12 + 0x50 SET_REG1 A = 0x62 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0012 = temp1 REG 0x0050 = E SUB1 0xAF = 0xFF - 0x50 CMP_UGT 0 = 0x0012 > 0x00AF SET_FLAG c = 0 C = A ---------------- REG 0x0062 = A SET_REG1 C = 0x62 A = B ---------------- REG 0x0007 = B SET_REG1 A = 0x07 A = adc.b(A, D, flag:c) ---------------- REG 0x0007 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0007 = 0x0007 + 0x0000 + 0 SET_REG1 A = 0x07 B = A ---------------- REG 0x0007 = A SET_REG1 B = 0x07 DE = DE - 1 ---------------- REG 0x0050 = DE SUB2 0x004F = 0x0050 - 0x0001 SET_REG2 DE = 0x004F goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x004F = E SUB1 0xB1 = 0x00 - 0x4F flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004F = E TEST_BIT 0 = bool(0x004F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004F = E TEST_BIT 0 = bool(0x004F & 0x0080) REG 0x0000 = A REG 0x004F = E SUB1 0xB1 = 0x00 - 0x4F TEST_BIT 1 = bool(0x00B1 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x004F = E SUB1 0xB1 = 0x00 - 0x4F TEST_BIT 1 = bool(0x00B1 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0062 = C SET_REG1 A = 0x62 temp1.b = A ---------------- REG 0x0062 = A SET_REG1 temp1 = 0x62 A = A + E ---------------- REG 0x0062 = A REG 0x004F = E ADD1 0xB1 = 0x62 + 0x4F SET_REG1 A = 0xB1 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0062 = temp1 REG 0x004F = E SUB1 0xB0 = 0xFF - 0x4F CMP_UGT 0 = 0x0062 > 0x00B0 SET_FLAG c = 0 C = A ---------------- REG 0x00B1 = A SET_REG1 C = 0xB1 A = B ---------------- REG 0x0007 = B SET_REG1 A = 0x07 A = adc.b(A, D, flag:c) ---------------- REG 0x0007 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0007 = 0x0007 + 0x0000 + 0 SET_REG1 A = 0x07 B = A ---------------- REG 0x0007 = A SET_REG1 B = 0x07 DE = DE - 1 ---------------- REG 0x004F = DE SUB2 0x004E = 0x004F - 0x0001 SET_REG2 DE = 0x004E goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x004E = E SUB1 0xB2 = 0x00 - 0x4E flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004E = E TEST_BIT 0 = bool(0x004E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004E = E TEST_BIT 0 = bool(0x004E & 0x0080) REG 0x0000 = A REG 0x004E = E SUB1 0xB2 = 0x00 - 0x4E TEST_BIT 1 = bool(0x00B2 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x004E = E SUB1 0xB2 = 0x00 - 0x4E TEST_BIT 1 = bool(0x00B2 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00B1 = C SET_REG1 A = 0xB1 temp1.b = A ---------------- REG 0x00B1 = A SET_REG1 temp1 = 0xB1 A = A + E ---------------- REG 0x00B1 = A REG 0x004E = E ADD1 0xFF = 0xB1 + 0x4E SET_REG1 A = 0xFF flag:c = temp1.b u> 0xff - E ---------------- REG 0x00B1 = temp1 REG 0x004E = E SUB1 0xB1 = 0xFF - 0x4E CMP_UGT 0 = 0x00B1 > 0x00B1 SET_FLAG c = 0 C = A ---------------- REG 0x00FF = A SET_REG1 C = 0xFF A = B ---------------- REG 0x0007 = B SET_REG1 A = 0x07 A = adc.b(A, D, flag:c) ---------------- REG 0x0007 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0007 = 0x0007 + 0x0000 + 0 SET_REG1 A = 0x07 B = A ---------------- REG 0x0007 = A SET_REG1 B = 0x07 DE = DE - 1 ---------------- REG 0x004E = DE SUB2 0x004D = 0x004E - 0x0001 SET_REG2 DE = 0x004D goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x004D = E SUB1 0xB3 = 0x00 - 0x4D flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004D = E TEST_BIT 0 = bool(0x004D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004D = E TEST_BIT 0 = bool(0x004D & 0x0080) REG 0x0000 = A REG 0x004D = E SUB1 0xB3 = 0x00 - 0x4D TEST_BIT 1 = bool(0x00B3 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x004D = E SUB1 0xB3 = 0x00 - 0x4D TEST_BIT 1 = bool(0x00B3 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00FF = C SET_REG1 A = 0xFF temp1.b = A ---------------- REG 0x00FF = A SET_REG1 temp1 = 0xFF A = A + E ---------------- REG 0x00FF = A REG 0x004D = E ADD1 0x4C = 0xFF + 0x4D SET_REG1 A = 0x4C flag:c = temp1.b u> 0xff - E ---------------- REG 0x00FF = temp1 REG 0x004D = E SUB1 0xB2 = 0xFF - 0x4D CMP_UGT 1 = 0x00FF > 0x00B2 SET_FLAG c = 1 C = A ---------------- REG 0x004C = A SET_REG1 C = 0x4C A = B ---------------- REG 0x0007 = B SET_REG1 A = 0x07 A = adc.b(A, D, flag:c) ---------------- REG 0x0007 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0008 = 0x0007 + 0x0000 + 1 SET_REG1 A = 0x08 B = A ---------------- REG 0x0008 = A SET_REG1 B = 0x08 DE = DE - 1 ---------------- REG 0x004D = DE SUB2 0x004C = 0x004D - 0x0001 SET_REG2 DE = 0x004C goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x004C = E SUB1 0xB4 = 0x00 - 0x4C flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004C = E TEST_BIT 0 = bool(0x004C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004C = E TEST_BIT 0 = bool(0x004C & 0x0080) REG 0x0000 = A REG 0x004C = E SUB1 0xB4 = 0x00 - 0x4C TEST_BIT 1 = bool(0x00B4 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x004C = E SUB1 0xB4 = 0x00 - 0x4C TEST_BIT 1 = bool(0x00B4 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x004C = C SET_REG1 A = 0x4C temp1.b = A ---------------- REG 0x004C = A SET_REG1 temp1 = 0x4C A = A + E ---------------- REG 0x004C = A REG 0x004C = E ADD1 0x98 = 0x4C + 0x4C SET_REG1 A = 0x98 flag:c = temp1.b u> 0xff - E ---------------- REG 0x004C = temp1 REG 0x004C = E SUB1 0xB3 = 0xFF - 0x4C CMP_UGT 0 = 0x004C > 0x00B3 SET_FLAG c = 0 C = A ---------------- REG 0x0098 = A SET_REG1 C = 0x98 A = B ---------------- REG 0x0008 = B SET_REG1 A = 0x08 A = adc.b(A, D, flag:c) ---------------- REG 0x0008 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0008 = 0x0008 + 0x0000 + 0 SET_REG1 A = 0x08 B = A ---------------- REG 0x0008 = A SET_REG1 B = 0x08 DE = DE - 1 ---------------- REG 0x004C = DE SUB2 0x004B = 0x004C - 0x0001 SET_REG2 DE = 0x004B goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x004B = E SUB1 0xB5 = 0x00 - 0x4B flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004B = E TEST_BIT 0 = bool(0x004B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004B = E TEST_BIT 0 = bool(0x004B & 0x0080) REG 0x0000 = A REG 0x004B = E SUB1 0xB5 = 0x00 - 0x4B TEST_BIT 1 = bool(0x00B5 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x004B = E SUB1 0xB5 = 0x00 - 0x4B TEST_BIT 1 = bool(0x00B5 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0098 = C SET_REG1 A = 0x98 temp1.b = A ---------------- REG 0x0098 = A SET_REG1 temp1 = 0x98 A = A + E ---------------- REG 0x0098 = A REG 0x004B = E ADD1 0xE3 = 0x98 + 0x4B SET_REG1 A = 0xE3 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0098 = temp1 REG 0x004B = E SUB1 0xB4 = 0xFF - 0x4B CMP_UGT 0 = 0x0098 > 0x00B4 SET_FLAG c = 0 C = A ---------------- REG 0x00E3 = A SET_REG1 C = 0xE3 A = B ---------------- REG 0x0008 = B SET_REG1 A = 0x08 A = adc.b(A, D, flag:c) ---------------- REG 0x0008 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0008 = 0x0008 + 0x0000 + 0 SET_REG1 A = 0x08 B = A ---------------- REG 0x0008 = A SET_REG1 B = 0x08 DE = DE - 1 ---------------- REG 0x004B = DE SUB2 0x004A = 0x004B - 0x0001 SET_REG2 DE = 0x004A goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x004A = E SUB1 0xB6 = 0x00 - 0x4A flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x004A = E TEST_BIT 0 = bool(0x004A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x004A = E TEST_BIT 0 = bool(0x004A & 0x0080) REG 0x0000 = A REG 0x004A = E SUB1 0xB6 = 0x00 - 0x4A TEST_BIT 1 = bool(0x00B6 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x004A = E SUB1 0xB6 = 0x00 - 0x4A TEST_BIT 1 = bool(0x00B6 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00E3 = C SET_REG1 A = 0xE3 temp1.b = A ---------------- REG 0x00E3 = A SET_REG1 temp1 = 0xE3 A = A + E ---------------- REG 0x00E3 = A REG 0x004A = E ADD1 0x2D = 0xE3 + 0x4A SET_REG1 A = 0x2D flag:c = temp1.b u> 0xff - E ---------------- REG 0x00E3 = temp1 REG 0x004A = E SUB1 0xB5 = 0xFF - 0x4A CMP_UGT 1 = 0x00E3 > 0x00B5 SET_FLAG c = 1 C = A ---------------- REG 0x002D = A SET_REG1 C = 0x2D A = B ---------------- REG 0x0008 = B SET_REG1 A = 0x08 A = adc.b(A, D, flag:c) ---------------- REG 0x0008 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0009 = 0x0008 + 0x0000 + 1 SET_REG1 A = 0x09 B = A ---------------- REG 0x0009 = A SET_REG1 B = 0x09 DE = DE - 1 ---------------- REG 0x004A = DE SUB2 0x0049 = 0x004A - 0x0001 SET_REG2 DE = 0x0049 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0049 = E SUB1 0xB7 = 0x00 - 0x49 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0049 = E TEST_BIT 0 = bool(0x0049 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0049 = E TEST_BIT 0 = bool(0x0049 & 0x0080) REG 0x0000 = A REG 0x0049 = E SUB1 0xB7 = 0x00 - 0x49 TEST_BIT 1 = bool(0x00B7 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0049 = E SUB1 0xB7 = 0x00 - 0x49 TEST_BIT 1 = bool(0x00B7 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x002D = C SET_REG1 A = 0x2D temp1.b = A ---------------- REG 0x002D = A SET_REG1 temp1 = 0x2D A = A + E ---------------- REG 0x002D = A REG 0x0049 = E ADD1 0x76 = 0x2D + 0x49 SET_REG1 A = 0x76 flag:c = temp1.b u> 0xff - E ---------------- REG 0x002D = temp1 REG 0x0049 = E SUB1 0xB6 = 0xFF - 0x49 CMP_UGT 0 = 0x002D > 0x00B6 SET_FLAG c = 0 C = A ---------------- REG 0x0076 = A SET_REG1 C = 0x76 A = B ---------------- REG 0x0009 = B SET_REG1 A = 0x09 A = adc.b(A, D, flag:c) ---------------- REG 0x0009 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0009 = 0x0009 + 0x0000 + 0 SET_REG1 A = 0x09 B = A ---------------- REG 0x0009 = A SET_REG1 B = 0x09 DE = DE - 1 ---------------- REG 0x0049 = DE SUB2 0x0048 = 0x0049 - 0x0001 SET_REG2 DE = 0x0048 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0048 = E SUB1 0xB8 = 0x00 - 0x48 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0048 = E TEST_BIT 0 = bool(0x0048 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0048 = E TEST_BIT 0 = bool(0x0048 & 0x0080) REG 0x0000 = A REG 0x0048 = E SUB1 0xB8 = 0x00 - 0x48 TEST_BIT 1 = bool(0x00B8 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0048 = E SUB1 0xB8 = 0x00 - 0x48 TEST_BIT 1 = bool(0x00B8 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0076 = C SET_REG1 A = 0x76 temp1.b = A ---------------- REG 0x0076 = A SET_REG1 temp1 = 0x76 A = A + E ---------------- REG 0x0076 = A REG 0x0048 = E ADD1 0xBE = 0x76 + 0x48 SET_REG1 A = 0xBE flag:c = temp1.b u> 0xff - E ---------------- REG 0x0076 = temp1 REG 0x0048 = E SUB1 0xB7 = 0xFF - 0x48 CMP_UGT 0 = 0x0076 > 0x00B7 SET_FLAG c = 0 C = A ---------------- REG 0x00BE = A SET_REG1 C = 0xBE A = B ---------------- REG 0x0009 = B SET_REG1 A = 0x09 A = adc.b(A, D, flag:c) ---------------- REG 0x0009 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0009 = 0x0009 + 0x0000 + 0 SET_REG1 A = 0x09 B = A ---------------- REG 0x0009 = A SET_REG1 B = 0x09 DE = DE - 1 ---------------- REG 0x0048 = DE SUB2 0x0047 = 0x0048 - 0x0001 SET_REG2 DE = 0x0047 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0047 = E SUB1 0xB9 = 0x00 - 0x47 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0047 = E TEST_BIT 0 = bool(0x0047 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0047 = E TEST_BIT 0 = bool(0x0047 & 0x0080) REG 0x0000 = A REG 0x0047 = E SUB1 0xB9 = 0x00 - 0x47 TEST_BIT 1 = bool(0x00B9 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0047 = E SUB1 0xB9 = 0x00 - 0x47 TEST_BIT 1 = bool(0x00B9 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00BE = C SET_REG1 A = 0xBE temp1.b = A ---------------- REG 0x00BE = A SET_REG1 temp1 = 0xBE A = A + E ---------------- REG 0x00BE = A REG 0x0047 = E ADD1 0x05 = 0xBE + 0x47 SET_REG1 A = 0x05 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00BE = temp1 REG 0x0047 = E SUB1 0xB8 = 0xFF - 0x47 CMP_UGT 1 = 0x00BE > 0x00B8 SET_FLAG c = 1 C = A ---------------- REG 0x0005 = A SET_REG1 C = 0x05 A = B ---------------- REG 0x0009 = B SET_REG1 A = 0x09 A = adc.b(A, D, flag:c) ---------------- REG 0x0009 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000A = 0x0009 + 0x0000 + 1 SET_REG1 A = 0x0A B = A ---------------- REG 0x000A = A SET_REG1 B = 0x0A DE = DE - 1 ---------------- REG 0x0047 = DE SUB2 0x0046 = 0x0047 - 0x0001 SET_REG2 DE = 0x0046 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0046 = E SUB1 0xBA = 0x00 - 0x46 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0046 = E TEST_BIT 0 = bool(0x0046 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0046 = E TEST_BIT 0 = bool(0x0046 & 0x0080) REG 0x0000 = A REG 0x0046 = E SUB1 0xBA = 0x00 - 0x46 TEST_BIT 1 = bool(0x00BA & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0046 = E SUB1 0xBA = 0x00 - 0x46 TEST_BIT 1 = bool(0x00BA & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0005 = C SET_REG1 A = 0x05 temp1.b = A ---------------- REG 0x0005 = A SET_REG1 temp1 = 0x05 A = A + E ---------------- REG 0x0005 = A REG 0x0046 = E ADD1 0x4B = 0x05 + 0x46 SET_REG1 A = 0x4B flag:c = temp1.b u> 0xff - E ---------------- REG 0x0005 = temp1 REG 0x0046 = E SUB1 0xB9 = 0xFF - 0x46 CMP_UGT 0 = 0x0005 > 0x00B9 SET_FLAG c = 0 C = A ---------------- REG 0x004B = A SET_REG1 C = 0x4B A = B ---------------- REG 0x000A = B SET_REG1 A = 0x0A A = adc.b(A, D, flag:c) ---------------- REG 0x000A = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000A = 0x000A + 0x0000 + 0 SET_REG1 A = 0x0A B = A ---------------- REG 0x000A = A SET_REG1 B = 0x0A DE = DE - 1 ---------------- REG 0x0046 = DE SUB2 0x0045 = 0x0046 - 0x0001 SET_REG2 DE = 0x0045 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0045 = E SUB1 0xBB = 0x00 - 0x45 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0045 = E TEST_BIT 0 = bool(0x0045 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0045 = E TEST_BIT 0 = bool(0x0045 & 0x0080) REG 0x0000 = A REG 0x0045 = E SUB1 0xBB = 0x00 - 0x45 TEST_BIT 1 = bool(0x00BB & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0045 = E SUB1 0xBB = 0x00 - 0x45 TEST_BIT 1 = bool(0x00BB & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x004B = C SET_REG1 A = 0x4B temp1.b = A ---------------- REG 0x004B = A SET_REG1 temp1 = 0x4B A = A + E ---------------- REG 0x004B = A REG 0x0045 = E ADD1 0x90 = 0x4B + 0x45 SET_REG1 A = 0x90 flag:c = temp1.b u> 0xff - E ---------------- REG 0x004B = temp1 REG 0x0045 = E SUB1 0xBA = 0xFF - 0x45 CMP_UGT 0 = 0x004B > 0x00BA SET_FLAG c = 0 C = A ---------------- REG 0x0090 = A SET_REG1 C = 0x90 A = B ---------------- REG 0x000A = B SET_REG1 A = 0x0A A = adc.b(A, D, flag:c) ---------------- REG 0x000A = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000A = 0x000A + 0x0000 + 0 SET_REG1 A = 0x0A B = A ---------------- REG 0x000A = A SET_REG1 B = 0x0A DE = DE - 1 ---------------- REG 0x0045 = DE SUB2 0x0044 = 0x0045 - 0x0001 SET_REG2 DE = 0x0044 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0044 = E SUB1 0xBC = 0x00 - 0x44 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0044 = E TEST_BIT 0 = bool(0x0044 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0044 = E TEST_BIT 0 = bool(0x0044 & 0x0080) REG 0x0000 = A REG 0x0044 = E SUB1 0xBC = 0x00 - 0x44 TEST_BIT 1 = bool(0x00BC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0044 = E SUB1 0xBC = 0x00 - 0x44 TEST_BIT 1 = bool(0x00BC & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0090 = C SET_REG1 A = 0x90 temp1.b = A ---------------- REG 0x0090 = A SET_REG1 temp1 = 0x90 A = A + E ---------------- REG 0x0090 = A REG 0x0044 = E ADD1 0xD4 = 0x90 + 0x44 SET_REG1 A = 0xD4 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0090 = temp1 REG 0x0044 = E SUB1 0xBB = 0xFF - 0x44 CMP_UGT 0 = 0x0090 > 0x00BB SET_FLAG c = 0 C = A ---------------- REG 0x00D4 = A SET_REG1 C = 0xD4 A = B ---------------- REG 0x000A = B SET_REG1 A = 0x0A A = adc.b(A, D, flag:c) ---------------- REG 0x000A = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000A = 0x000A + 0x0000 + 0 SET_REG1 A = 0x0A B = A ---------------- REG 0x000A = A SET_REG1 B = 0x0A DE = DE - 1 ---------------- REG 0x0044 = DE SUB2 0x0043 = 0x0044 - 0x0001 SET_REG2 DE = 0x0043 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0043 = E SUB1 0xBD = 0x00 - 0x43 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0043 = E TEST_BIT 0 = bool(0x0043 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0043 = E TEST_BIT 0 = bool(0x0043 & 0x0080) REG 0x0000 = A REG 0x0043 = E SUB1 0xBD = 0x00 - 0x43 TEST_BIT 1 = bool(0x00BD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0043 = E SUB1 0xBD = 0x00 - 0x43 TEST_BIT 1 = bool(0x00BD & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00D4 = C SET_REG1 A = 0xD4 temp1.b = A ---------------- REG 0x00D4 = A SET_REG1 temp1 = 0xD4 A = A + E ---------------- REG 0x00D4 = A REG 0x0043 = E ADD1 0x17 = 0xD4 + 0x43 SET_REG1 A = 0x17 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00D4 = temp1 REG 0x0043 = E SUB1 0xBC = 0xFF - 0x43 CMP_UGT 1 = 0x00D4 > 0x00BC SET_FLAG c = 1 C = A ---------------- REG 0x0017 = A SET_REG1 C = 0x17 A = B ---------------- REG 0x000A = B SET_REG1 A = 0x0A A = adc.b(A, D, flag:c) ---------------- REG 0x000A = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000B = 0x000A + 0x0000 + 1 SET_REG1 A = 0x0B B = A ---------------- REG 0x000B = A SET_REG1 B = 0x0B DE = DE - 1 ---------------- REG 0x0043 = DE SUB2 0x0042 = 0x0043 - 0x0001 SET_REG2 DE = 0x0042 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0042 = E SUB1 0xBE = 0x00 - 0x42 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0042 = E TEST_BIT 0 = bool(0x0042 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0042 = E TEST_BIT 0 = bool(0x0042 & 0x0080) REG 0x0000 = A REG 0x0042 = E SUB1 0xBE = 0x00 - 0x42 TEST_BIT 1 = bool(0x00BE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0042 = E SUB1 0xBE = 0x00 - 0x42 TEST_BIT 1 = bool(0x00BE & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0017 = C SET_REG1 A = 0x17 temp1.b = A ---------------- REG 0x0017 = A SET_REG1 temp1 = 0x17 A = A + E ---------------- REG 0x0017 = A REG 0x0042 = E ADD1 0x59 = 0x17 + 0x42 SET_REG1 A = 0x59 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0017 = temp1 REG 0x0042 = E SUB1 0xBD = 0xFF - 0x42 CMP_UGT 0 = 0x0017 > 0x00BD SET_FLAG c = 0 C = A ---------------- REG 0x0059 = A SET_REG1 C = 0x59 A = B ---------------- REG 0x000B = B SET_REG1 A = 0x0B A = adc.b(A, D, flag:c) ---------------- REG 0x000B = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000B = 0x000B + 0x0000 + 0 SET_REG1 A = 0x0B B = A ---------------- REG 0x000B = A SET_REG1 B = 0x0B DE = DE - 1 ---------------- REG 0x0042 = DE SUB2 0x0041 = 0x0042 - 0x0001 SET_REG2 DE = 0x0041 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0041 = E SUB1 0xBF = 0x00 - 0x41 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0041 = E TEST_BIT 0 = bool(0x0041 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0041 = E TEST_BIT 0 = bool(0x0041 & 0x0080) REG 0x0000 = A REG 0x0041 = E SUB1 0xBF = 0x00 - 0x41 TEST_BIT 1 = bool(0x00BF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0041 = E SUB1 0xBF = 0x00 - 0x41 TEST_BIT 1 = bool(0x00BF & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0059 = C SET_REG1 A = 0x59 temp1.b = A ---------------- REG 0x0059 = A SET_REG1 temp1 = 0x59 A = A + E ---------------- REG 0x0059 = A REG 0x0041 = E ADD1 0x9A = 0x59 + 0x41 SET_REG1 A = 0x9A flag:c = temp1.b u> 0xff - E ---------------- REG 0x0059 = temp1 REG 0x0041 = E SUB1 0xBE = 0xFF - 0x41 CMP_UGT 0 = 0x0059 > 0x00BE SET_FLAG c = 0 C = A ---------------- REG 0x009A = A SET_REG1 C = 0x9A A = B ---------------- REG 0x000B = B SET_REG1 A = 0x0B A = adc.b(A, D, flag:c) ---------------- REG 0x000B = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000B = 0x000B + 0x0000 + 0 SET_REG1 A = 0x0B B = A ---------------- REG 0x000B = A SET_REG1 B = 0x0B DE = DE - 1 ---------------- REG 0x0041 = DE SUB2 0x0040 = 0x0041 - 0x0001 SET_REG2 DE = 0x0040 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0040 = E SUB1 0xC0 = 0x00 - 0x40 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0040 = E TEST_BIT 0 = bool(0x0040 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0040 = E TEST_BIT 0 = bool(0x0040 & 0x0080) REG 0x0000 = A REG 0x0040 = E SUB1 0xC0 = 0x00 - 0x40 TEST_BIT 1 = bool(0x00C0 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0040 = E SUB1 0xC0 = 0x00 - 0x40 TEST_BIT 1 = bool(0x00C0 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x009A = C SET_REG1 A = 0x9A temp1.b = A ---------------- REG 0x009A = A SET_REG1 temp1 = 0x9A A = A + E ---------------- REG 0x009A = A REG 0x0040 = E ADD1 0xDA = 0x9A + 0x40 SET_REG1 A = 0xDA flag:c = temp1.b u> 0xff - E ---------------- REG 0x009A = temp1 REG 0x0040 = E SUB1 0xBF = 0xFF - 0x40 CMP_UGT 0 = 0x009A > 0x00BF SET_FLAG c = 0 C = A ---------------- REG 0x00DA = A SET_REG1 C = 0xDA A = B ---------------- REG 0x000B = B SET_REG1 A = 0x0B A = adc.b(A, D, flag:c) ---------------- REG 0x000B = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000B = 0x000B + 0x0000 + 0 SET_REG1 A = 0x0B B = A ---------------- REG 0x000B = A SET_REG1 B = 0x0B DE = DE - 1 ---------------- REG 0x0040 = DE SUB2 0x003F = 0x0040 - 0x0001 SET_REG2 DE = 0x003F goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x003F = E SUB1 0xC1 = 0x00 - 0x3F flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003F = E TEST_BIT 0 = bool(0x003F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003F = E TEST_BIT 0 = bool(0x003F & 0x0080) REG 0x0000 = A REG 0x003F = E SUB1 0xC1 = 0x00 - 0x3F TEST_BIT 1 = bool(0x00C1 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x003F = E SUB1 0xC1 = 0x00 - 0x3F TEST_BIT 1 = bool(0x00C1 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00DA = C SET_REG1 A = 0xDA temp1.b = A ---------------- REG 0x00DA = A SET_REG1 temp1 = 0xDA A = A + E ---------------- REG 0x00DA = A REG 0x003F = E ADD1 0x19 = 0xDA + 0x3F SET_REG1 A = 0x19 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00DA = temp1 REG 0x003F = E SUB1 0xC0 = 0xFF - 0x3F CMP_UGT 1 = 0x00DA > 0x00C0 SET_FLAG c = 1 C = A ---------------- REG 0x0019 = A SET_REG1 C = 0x19 A = B ---------------- REG 0x000B = B SET_REG1 A = 0x0B A = adc.b(A, D, flag:c) ---------------- REG 0x000B = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000C = 0x000B + 0x0000 + 1 SET_REG1 A = 0x0C B = A ---------------- REG 0x000C = A SET_REG1 B = 0x0C DE = DE - 1 ---------------- REG 0x003F = DE SUB2 0x003E = 0x003F - 0x0001 SET_REG2 DE = 0x003E goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x003E = E SUB1 0xC2 = 0x00 - 0x3E flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003E = E TEST_BIT 0 = bool(0x003E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003E = E TEST_BIT 0 = bool(0x003E & 0x0080) REG 0x0000 = A REG 0x003E = E SUB1 0xC2 = 0x00 - 0x3E TEST_BIT 1 = bool(0x00C2 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x003E = E SUB1 0xC2 = 0x00 - 0x3E TEST_BIT 1 = bool(0x00C2 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0019 = C SET_REG1 A = 0x19 temp1.b = A ---------------- REG 0x0019 = A SET_REG1 temp1 = 0x19 A = A + E ---------------- REG 0x0019 = A REG 0x003E = E ADD1 0x57 = 0x19 + 0x3E SET_REG1 A = 0x57 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0019 = temp1 REG 0x003E = E SUB1 0xC1 = 0xFF - 0x3E CMP_UGT 0 = 0x0019 > 0x00C1 SET_FLAG c = 0 C = A ---------------- REG 0x0057 = A SET_REG1 C = 0x57 A = B ---------------- REG 0x000C = B SET_REG1 A = 0x0C A = adc.b(A, D, flag:c) ---------------- REG 0x000C = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000C = 0x000C + 0x0000 + 0 SET_REG1 A = 0x0C B = A ---------------- REG 0x000C = A SET_REG1 B = 0x0C DE = DE - 1 ---------------- REG 0x003E = DE SUB2 0x003D = 0x003E - 0x0001 SET_REG2 DE = 0x003D goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x003D = E SUB1 0xC3 = 0x00 - 0x3D flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003D = E TEST_BIT 0 = bool(0x003D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003D = E TEST_BIT 0 = bool(0x003D & 0x0080) REG 0x0000 = A REG 0x003D = E SUB1 0xC3 = 0x00 - 0x3D TEST_BIT 1 = bool(0x00C3 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x003D = E SUB1 0xC3 = 0x00 - 0x3D TEST_BIT 1 = bool(0x00C3 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0057 = C SET_REG1 A = 0x57 temp1.b = A ---------------- REG 0x0057 = A SET_REG1 temp1 = 0x57 A = A + E ---------------- REG 0x0057 = A REG 0x003D = E ADD1 0x94 = 0x57 + 0x3D SET_REG1 A = 0x94 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0057 = temp1 REG 0x003D = E SUB1 0xC2 = 0xFF - 0x3D CMP_UGT 0 = 0x0057 > 0x00C2 SET_FLAG c = 0 C = A ---------------- REG 0x0094 = A SET_REG1 C = 0x94 A = B ---------------- REG 0x000C = B SET_REG1 A = 0x0C A = adc.b(A, D, flag:c) ---------------- REG 0x000C = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000C = 0x000C + 0x0000 + 0 SET_REG1 A = 0x0C B = A ---------------- REG 0x000C = A SET_REG1 B = 0x0C DE = DE - 1 ---------------- REG 0x003D = DE SUB2 0x003C = 0x003D - 0x0001 SET_REG2 DE = 0x003C goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x003C = E SUB1 0xC4 = 0x00 - 0x3C flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003C = E TEST_BIT 0 = bool(0x003C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003C = E TEST_BIT 0 = bool(0x003C & 0x0080) REG 0x0000 = A REG 0x003C = E SUB1 0xC4 = 0x00 - 0x3C TEST_BIT 1 = bool(0x00C4 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x003C = E SUB1 0xC4 = 0x00 - 0x3C TEST_BIT 1 = bool(0x00C4 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0094 = C SET_REG1 A = 0x94 temp1.b = A ---------------- REG 0x0094 = A SET_REG1 temp1 = 0x94 A = A + E ---------------- REG 0x0094 = A REG 0x003C = E ADD1 0xD0 = 0x94 + 0x3C SET_REG1 A = 0xD0 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0094 = temp1 REG 0x003C = E SUB1 0xC3 = 0xFF - 0x3C CMP_UGT 0 = 0x0094 > 0x00C3 SET_FLAG c = 0 C = A ---------------- REG 0x00D0 = A SET_REG1 C = 0xD0 A = B ---------------- REG 0x000C = B SET_REG1 A = 0x0C A = adc.b(A, D, flag:c) ---------------- REG 0x000C = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000C = 0x000C + 0x0000 + 0 SET_REG1 A = 0x0C B = A ---------------- REG 0x000C = A SET_REG1 B = 0x0C DE = DE - 1 ---------------- REG 0x003C = DE SUB2 0x003B = 0x003C - 0x0001 SET_REG2 DE = 0x003B goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x003B = E SUB1 0xC5 = 0x00 - 0x3B flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003B = E TEST_BIT 0 = bool(0x003B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003B = E TEST_BIT 0 = bool(0x003B & 0x0080) REG 0x0000 = A REG 0x003B = E SUB1 0xC5 = 0x00 - 0x3B TEST_BIT 1 = bool(0x00C5 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x003B = E SUB1 0xC5 = 0x00 - 0x3B TEST_BIT 1 = bool(0x00C5 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00D0 = C SET_REG1 A = 0xD0 temp1.b = A ---------------- REG 0x00D0 = A SET_REG1 temp1 = 0xD0 A = A + E ---------------- REG 0x00D0 = A REG 0x003B = E ADD1 0x0B = 0xD0 + 0x3B SET_REG1 A = 0x0B flag:c = temp1.b u> 0xff - E ---------------- REG 0x00D0 = temp1 REG 0x003B = E SUB1 0xC4 = 0xFF - 0x3B CMP_UGT 1 = 0x00D0 > 0x00C4 SET_FLAG c = 1 C = A ---------------- REG 0x000B = A SET_REG1 C = 0x0B A = B ---------------- REG 0x000C = B SET_REG1 A = 0x0C A = adc.b(A, D, flag:c) ---------------- REG 0x000C = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000D = 0x000C + 0x0000 + 1 SET_REG1 A = 0x0D B = A ---------------- REG 0x000D = A SET_REG1 B = 0x0D DE = DE - 1 ---------------- REG 0x003B = DE SUB2 0x003A = 0x003B - 0x0001 SET_REG2 DE = 0x003A goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x003A = E SUB1 0xC6 = 0x00 - 0x3A flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x003A = E TEST_BIT 0 = bool(0x003A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x003A = E TEST_BIT 0 = bool(0x003A & 0x0080) REG 0x0000 = A REG 0x003A = E SUB1 0xC6 = 0x00 - 0x3A TEST_BIT 1 = bool(0x00C6 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x003A = E SUB1 0xC6 = 0x00 - 0x3A TEST_BIT 1 = bool(0x00C6 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x000B = C SET_REG1 A = 0x0B temp1.b = A ---------------- REG 0x000B = A SET_REG1 temp1 = 0x0B A = A + E ---------------- REG 0x000B = A REG 0x003A = E ADD1 0x45 = 0x0B + 0x3A SET_REG1 A = 0x45 flag:c = temp1.b u> 0xff - E ---------------- REG 0x000B = temp1 REG 0x003A = E SUB1 0xC5 = 0xFF - 0x3A CMP_UGT 0 = 0x000B > 0x00C5 SET_FLAG c = 0 C = A ---------------- REG 0x0045 = A SET_REG1 C = 0x45 A = B ---------------- REG 0x000D = B SET_REG1 A = 0x0D A = adc.b(A, D, flag:c) ---------------- REG 0x000D = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000D = 0x000D + 0x0000 + 0 SET_REG1 A = 0x0D B = A ---------------- REG 0x000D = A SET_REG1 B = 0x0D DE = DE - 1 ---------------- REG 0x003A = DE SUB2 0x0039 = 0x003A - 0x0001 SET_REG2 DE = 0x0039 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0039 = E SUB1 0xC7 = 0x00 - 0x39 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0039 = E TEST_BIT 0 = bool(0x0039 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0039 = E TEST_BIT 0 = bool(0x0039 & 0x0080) REG 0x0000 = A REG 0x0039 = E SUB1 0xC7 = 0x00 - 0x39 TEST_BIT 1 = bool(0x00C7 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0039 = E SUB1 0xC7 = 0x00 - 0x39 TEST_BIT 1 = bool(0x00C7 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0045 = C SET_REG1 A = 0x45 temp1.b = A ---------------- REG 0x0045 = A SET_REG1 temp1 = 0x45 A = A + E ---------------- REG 0x0045 = A REG 0x0039 = E ADD1 0x7E = 0x45 + 0x39 SET_REG1 A = 0x7E flag:c = temp1.b u> 0xff - E ---------------- REG 0x0045 = temp1 REG 0x0039 = E SUB1 0xC6 = 0xFF - 0x39 CMP_UGT 0 = 0x0045 > 0x00C6 SET_FLAG c = 0 C = A ---------------- REG 0x007E = A SET_REG1 C = 0x7E A = B ---------------- REG 0x000D = B SET_REG1 A = 0x0D A = adc.b(A, D, flag:c) ---------------- REG 0x000D = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000D = 0x000D + 0x0000 + 0 SET_REG1 A = 0x0D B = A ---------------- REG 0x000D = A SET_REG1 B = 0x0D DE = DE - 1 ---------------- REG 0x0039 = DE SUB2 0x0038 = 0x0039 - 0x0001 SET_REG2 DE = 0x0038 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0038 = E SUB1 0xC8 = 0x00 - 0x38 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0038 = E TEST_BIT 0 = bool(0x0038 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0038 = E TEST_BIT 0 = bool(0x0038 & 0x0080) REG 0x0000 = A REG 0x0038 = E SUB1 0xC8 = 0x00 - 0x38 TEST_BIT 1 = bool(0x00C8 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0038 = E SUB1 0xC8 = 0x00 - 0x38 TEST_BIT 1 = bool(0x00C8 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x007E = C SET_REG1 A = 0x7E temp1.b = A ---------------- REG 0x007E = A SET_REG1 temp1 = 0x7E A = A + E ---------------- REG 0x007E = A REG 0x0038 = E ADD1 0xB6 = 0x7E + 0x38 SET_REG1 A = 0xB6 flag:c = temp1.b u> 0xff - E ---------------- REG 0x007E = temp1 REG 0x0038 = E SUB1 0xC7 = 0xFF - 0x38 CMP_UGT 0 = 0x007E > 0x00C7 SET_FLAG c = 0 C = A ---------------- REG 0x00B6 = A SET_REG1 C = 0xB6 A = B ---------------- REG 0x000D = B SET_REG1 A = 0x0D A = adc.b(A, D, flag:c) ---------------- REG 0x000D = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000D = 0x000D + 0x0000 + 0 SET_REG1 A = 0x0D B = A ---------------- REG 0x000D = A SET_REG1 B = 0x0D DE = DE - 1 ---------------- REG 0x0038 = DE SUB2 0x0037 = 0x0038 - 0x0001 SET_REG2 DE = 0x0037 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0037 = E SUB1 0xC9 = 0x00 - 0x37 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0037 = E TEST_BIT 0 = bool(0x0037 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0037 = E TEST_BIT 0 = bool(0x0037 & 0x0080) REG 0x0000 = A REG 0x0037 = E SUB1 0xC9 = 0x00 - 0x37 TEST_BIT 1 = bool(0x00C9 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0037 = E SUB1 0xC9 = 0x00 - 0x37 TEST_BIT 1 = bool(0x00C9 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00B6 = C SET_REG1 A = 0xB6 temp1.b = A ---------------- REG 0x00B6 = A SET_REG1 temp1 = 0xB6 A = A + E ---------------- REG 0x00B6 = A REG 0x0037 = E ADD1 0xED = 0xB6 + 0x37 SET_REG1 A = 0xED flag:c = temp1.b u> 0xff - E ---------------- REG 0x00B6 = temp1 REG 0x0037 = E SUB1 0xC8 = 0xFF - 0x37 CMP_UGT 0 = 0x00B6 > 0x00C8 SET_FLAG c = 0 C = A ---------------- REG 0x00ED = A SET_REG1 C = 0xED A = B ---------------- REG 0x000D = B SET_REG1 A = 0x0D A = adc.b(A, D, flag:c) ---------------- REG 0x000D = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000D = 0x000D + 0x0000 + 0 SET_REG1 A = 0x0D B = A ---------------- REG 0x000D = A SET_REG1 B = 0x0D DE = DE - 1 ---------------- REG 0x0037 = DE SUB2 0x0036 = 0x0037 - 0x0001 SET_REG2 DE = 0x0036 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0036 = E SUB1 0xCA = 0x00 - 0x36 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0036 = E TEST_BIT 0 = bool(0x0036 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0036 = E TEST_BIT 0 = bool(0x0036 & 0x0080) REG 0x0000 = A REG 0x0036 = E SUB1 0xCA = 0x00 - 0x36 TEST_BIT 1 = bool(0x00CA & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0036 = E SUB1 0xCA = 0x00 - 0x36 TEST_BIT 1 = bool(0x00CA & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00ED = C SET_REG1 A = 0xED temp1.b = A ---------------- REG 0x00ED = A SET_REG1 temp1 = 0xED A = A + E ---------------- REG 0x00ED = A REG 0x0036 = E ADD1 0x23 = 0xED + 0x36 SET_REG1 A = 0x23 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00ED = temp1 REG 0x0036 = E SUB1 0xC9 = 0xFF - 0x36 CMP_UGT 1 = 0x00ED > 0x00C9 SET_FLAG c = 1 C = A ---------------- REG 0x0023 = A SET_REG1 C = 0x23 A = B ---------------- REG 0x000D = B SET_REG1 A = 0x0D A = adc.b(A, D, flag:c) ---------------- REG 0x000D = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000E = 0x000D + 0x0000 + 1 SET_REG1 A = 0x0E B = A ---------------- REG 0x000E = A SET_REG1 B = 0x0E DE = DE - 1 ---------------- REG 0x0036 = DE SUB2 0x0035 = 0x0036 - 0x0001 SET_REG2 DE = 0x0035 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0035 = E SUB1 0xCB = 0x00 - 0x35 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0035 = E TEST_BIT 0 = bool(0x0035 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0035 = E TEST_BIT 0 = bool(0x0035 & 0x0080) REG 0x0000 = A REG 0x0035 = E SUB1 0xCB = 0x00 - 0x35 TEST_BIT 1 = bool(0x00CB & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0035 = E SUB1 0xCB = 0x00 - 0x35 TEST_BIT 1 = bool(0x00CB & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0023 = C SET_REG1 A = 0x23 temp1.b = A ---------------- REG 0x0023 = A SET_REG1 temp1 = 0x23 A = A + E ---------------- REG 0x0023 = A REG 0x0035 = E ADD1 0x58 = 0x23 + 0x35 SET_REG1 A = 0x58 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0023 = temp1 REG 0x0035 = E SUB1 0xCA = 0xFF - 0x35 CMP_UGT 0 = 0x0023 > 0x00CA SET_FLAG c = 0 C = A ---------------- REG 0x0058 = A SET_REG1 C = 0x58 A = B ---------------- REG 0x000E = B SET_REG1 A = 0x0E A = adc.b(A, D, flag:c) ---------------- REG 0x000E = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000E = 0x000E + 0x0000 + 0 SET_REG1 A = 0x0E B = A ---------------- REG 0x000E = A SET_REG1 B = 0x0E DE = DE - 1 ---------------- REG 0x0035 = DE SUB2 0x0034 = 0x0035 - 0x0001 SET_REG2 DE = 0x0034 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0034 = E SUB1 0xCC = 0x00 - 0x34 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0034 = E TEST_BIT 0 = bool(0x0034 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0034 = E TEST_BIT 0 = bool(0x0034 & 0x0080) REG 0x0000 = A REG 0x0034 = E SUB1 0xCC = 0x00 - 0x34 TEST_BIT 1 = bool(0x00CC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0034 = E SUB1 0xCC = 0x00 - 0x34 TEST_BIT 1 = bool(0x00CC & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0058 = C SET_REG1 A = 0x58 temp1.b = A ---------------- REG 0x0058 = A SET_REG1 temp1 = 0x58 A = A + E ---------------- REG 0x0058 = A REG 0x0034 = E ADD1 0x8C = 0x58 + 0x34 SET_REG1 A = 0x8C flag:c = temp1.b u> 0xff - E ---------------- REG 0x0058 = temp1 REG 0x0034 = E SUB1 0xCB = 0xFF - 0x34 CMP_UGT 0 = 0x0058 > 0x00CB SET_FLAG c = 0 C = A ---------------- REG 0x008C = A SET_REG1 C = 0x8C A = B ---------------- REG 0x000E = B SET_REG1 A = 0x0E A = adc.b(A, D, flag:c) ---------------- REG 0x000E = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000E = 0x000E + 0x0000 + 0 SET_REG1 A = 0x0E B = A ---------------- REG 0x000E = A SET_REG1 B = 0x0E DE = DE - 1 ---------------- REG 0x0034 = DE SUB2 0x0033 = 0x0034 - 0x0001 SET_REG2 DE = 0x0033 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0033 = E SUB1 0xCD = 0x00 - 0x33 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0033 = E TEST_BIT 0 = bool(0x0033 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0033 = E TEST_BIT 0 = bool(0x0033 & 0x0080) REG 0x0000 = A REG 0x0033 = E SUB1 0xCD = 0x00 - 0x33 TEST_BIT 1 = bool(0x00CD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0033 = E SUB1 0xCD = 0x00 - 0x33 TEST_BIT 1 = bool(0x00CD & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x008C = C SET_REG1 A = 0x8C temp1.b = A ---------------- REG 0x008C = A SET_REG1 temp1 = 0x8C A = A + E ---------------- REG 0x008C = A REG 0x0033 = E ADD1 0xBF = 0x8C + 0x33 SET_REG1 A = 0xBF flag:c = temp1.b u> 0xff - E ---------------- REG 0x008C = temp1 REG 0x0033 = E SUB1 0xCC = 0xFF - 0x33 CMP_UGT 0 = 0x008C > 0x00CC SET_FLAG c = 0 C = A ---------------- REG 0x00BF = A SET_REG1 C = 0xBF A = B ---------------- REG 0x000E = B SET_REG1 A = 0x0E A = adc.b(A, D, flag:c) ---------------- REG 0x000E = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000E = 0x000E + 0x0000 + 0 SET_REG1 A = 0x0E B = A ---------------- REG 0x000E = A SET_REG1 B = 0x0E DE = DE - 1 ---------------- REG 0x0033 = DE SUB2 0x0032 = 0x0033 - 0x0001 SET_REG2 DE = 0x0032 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0032 = E SUB1 0xCE = 0x00 - 0x32 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0032 = E TEST_BIT 0 = bool(0x0032 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0032 = E TEST_BIT 0 = bool(0x0032 & 0x0080) REG 0x0000 = A REG 0x0032 = E SUB1 0xCE = 0x00 - 0x32 TEST_BIT 1 = bool(0x00CE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0032 = E SUB1 0xCE = 0x00 - 0x32 TEST_BIT 1 = bool(0x00CE & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00BF = C SET_REG1 A = 0xBF temp1.b = A ---------------- REG 0x00BF = A SET_REG1 temp1 = 0xBF A = A + E ---------------- REG 0x00BF = A REG 0x0032 = E ADD1 0xF1 = 0xBF + 0x32 SET_REG1 A = 0xF1 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00BF = temp1 REG 0x0032 = E SUB1 0xCD = 0xFF - 0x32 CMP_UGT 0 = 0x00BF > 0x00CD SET_FLAG c = 0 C = A ---------------- REG 0x00F1 = A SET_REG1 C = 0xF1 A = B ---------------- REG 0x000E = B SET_REG1 A = 0x0E A = adc.b(A, D, flag:c) ---------------- REG 0x000E = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000E = 0x000E + 0x0000 + 0 SET_REG1 A = 0x0E B = A ---------------- REG 0x000E = A SET_REG1 B = 0x0E DE = DE - 1 ---------------- REG 0x0032 = DE SUB2 0x0031 = 0x0032 - 0x0001 SET_REG2 DE = 0x0031 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0031 = E SUB1 0xCF = 0x00 - 0x31 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0031 = E TEST_BIT 0 = bool(0x0031 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0031 = E TEST_BIT 0 = bool(0x0031 & 0x0080) REG 0x0000 = A REG 0x0031 = E SUB1 0xCF = 0x00 - 0x31 TEST_BIT 1 = bool(0x00CF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0031 = E SUB1 0xCF = 0x00 - 0x31 TEST_BIT 1 = bool(0x00CF & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00F1 = C SET_REG1 A = 0xF1 temp1.b = A ---------------- REG 0x00F1 = A SET_REG1 temp1 = 0xF1 A = A + E ---------------- REG 0x00F1 = A REG 0x0031 = E ADD1 0x22 = 0xF1 + 0x31 SET_REG1 A = 0x22 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00F1 = temp1 REG 0x0031 = E SUB1 0xCE = 0xFF - 0x31 CMP_UGT 1 = 0x00F1 > 0x00CE SET_FLAG c = 1 C = A ---------------- REG 0x0022 = A SET_REG1 C = 0x22 A = B ---------------- REG 0x000E = B SET_REG1 A = 0x0E A = adc.b(A, D, flag:c) ---------------- REG 0x000E = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x000F = 0x000E + 0x0000 + 1 SET_REG1 A = 0x0F B = A ---------------- REG 0x000F = A SET_REG1 B = 0x0F DE = DE - 1 ---------------- REG 0x0031 = DE SUB2 0x0030 = 0x0031 - 0x0001 SET_REG2 DE = 0x0030 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0030 = E SUB1 0xD0 = 0x00 - 0x30 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0030 = E TEST_BIT 0 = bool(0x0030 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0030 = E TEST_BIT 0 = bool(0x0030 & 0x0080) REG 0x0000 = A REG 0x0030 = E SUB1 0xD0 = 0x00 - 0x30 TEST_BIT 1 = bool(0x00D0 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0030 = E SUB1 0xD0 = 0x00 - 0x30 TEST_BIT 1 = bool(0x00D0 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0022 = C SET_REG1 A = 0x22 temp1.b = A ---------------- REG 0x0022 = A SET_REG1 temp1 = 0x22 A = A + E ---------------- REG 0x0022 = A REG 0x0030 = E ADD1 0x52 = 0x22 + 0x30 SET_REG1 A = 0x52 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0022 = temp1 REG 0x0030 = E SUB1 0xCF = 0xFF - 0x30 CMP_UGT 0 = 0x0022 > 0x00CF SET_FLAG c = 0 C = A ---------------- REG 0x0052 = A SET_REG1 C = 0x52 A = B ---------------- REG 0x000F = B SET_REG1 A = 0x0F A = adc.b(A, D, flag:c) ---------------- REG 0x000F = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000F = 0x000F + 0x0000 + 0 SET_REG1 A = 0x0F B = A ---------------- REG 0x000F = A SET_REG1 B = 0x0F DE = DE - 1 ---------------- REG 0x0030 = DE SUB2 0x002F = 0x0030 - 0x0001 SET_REG2 DE = 0x002F goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x002F = E SUB1 0xD1 = 0x00 - 0x2F flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002F = E TEST_BIT 0 = bool(0x002F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002F = E TEST_BIT 0 = bool(0x002F & 0x0080) REG 0x0000 = A REG 0x002F = E SUB1 0xD1 = 0x00 - 0x2F TEST_BIT 1 = bool(0x00D1 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x002F = E SUB1 0xD1 = 0x00 - 0x2F TEST_BIT 1 = bool(0x00D1 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0052 = C SET_REG1 A = 0x52 temp1.b = A ---------------- REG 0x0052 = A SET_REG1 temp1 = 0x52 A = A + E ---------------- REG 0x0052 = A REG 0x002F = E ADD1 0x81 = 0x52 + 0x2F SET_REG1 A = 0x81 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0052 = temp1 REG 0x002F = E SUB1 0xD0 = 0xFF - 0x2F CMP_UGT 0 = 0x0052 > 0x00D0 SET_FLAG c = 0 C = A ---------------- REG 0x0081 = A SET_REG1 C = 0x81 A = B ---------------- REG 0x000F = B SET_REG1 A = 0x0F A = adc.b(A, D, flag:c) ---------------- REG 0x000F = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000F = 0x000F + 0x0000 + 0 SET_REG1 A = 0x0F B = A ---------------- REG 0x000F = A SET_REG1 B = 0x0F DE = DE - 1 ---------------- REG 0x002F = DE SUB2 0x002E = 0x002F - 0x0001 SET_REG2 DE = 0x002E goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x002E = E SUB1 0xD2 = 0x00 - 0x2E flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002E = E TEST_BIT 0 = bool(0x002E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002E = E TEST_BIT 0 = bool(0x002E & 0x0080) REG 0x0000 = A REG 0x002E = E SUB1 0xD2 = 0x00 - 0x2E TEST_BIT 1 = bool(0x00D2 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x002E = E SUB1 0xD2 = 0x00 - 0x2E TEST_BIT 1 = bool(0x00D2 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0081 = C SET_REG1 A = 0x81 temp1.b = A ---------------- REG 0x0081 = A SET_REG1 temp1 = 0x81 A = A + E ---------------- REG 0x0081 = A REG 0x002E = E ADD1 0xAF = 0x81 + 0x2E SET_REG1 A = 0xAF flag:c = temp1.b u> 0xff - E ---------------- REG 0x0081 = temp1 REG 0x002E = E SUB1 0xD1 = 0xFF - 0x2E CMP_UGT 0 = 0x0081 > 0x00D1 SET_FLAG c = 0 C = A ---------------- REG 0x00AF = A SET_REG1 C = 0xAF A = B ---------------- REG 0x000F = B SET_REG1 A = 0x0F A = adc.b(A, D, flag:c) ---------------- REG 0x000F = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000F = 0x000F + 0x0000 + 0 SET_REG1 A = 0x0F B = A ---------------- REG 0x000F = A SET_REG1 B = 0x0F DE = DE - 1 ---------------- REG 0x002E = DE SUB2 0x002D = 0x002E - 0x0001 SET_REG2 DE = 0x002D goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x002D = E SUB1 0xD3 = 0x00 - 0x2D flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002D = E TEST_BIT 0 = bool(0x002D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002D = E TEST_BIT 0 = bool(0x002D & 0x0080) REG 0x0000 = A REG 0x002D = E SUB1 0xD3 = 0x00 - 0x2D TEST_BIT 1 = bool(0x00D3 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x002D = E SUB1 0xD3 = 0x00 - 0x2D TEST_BIT 1 = bool(0x00D3 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00AF = C SET_REG1 A = 0xAF temp1.b = A ---------------- REG 0x00AF = A SET_REG1 temp1 = 0xAF A = A + E ---------------- REG 0x00AF = A REG 0x002D = E ADD1 0xDC = 0xAF + 0x2D SET_REG1 A = 0xDC flag:c = temp1.b u> 0xff - E ---------------- REG 0x00AF = temp1 REG 0x002D = E SUB1 0xD2 = 0xFF - 0x2D CMP_UGT 0 = 0x00AF > 0x00D2 SET_FLAG c = 0 C = A ---------------- REG 0x00DC = A SET_REG1 C = 0xDC A = B ---------------- REG 0x000F = B SET_REG1 A = 0x0F A = adc.b(A, D, flag:c) ---------------- REG 0x000F = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x000F = 0x000F + 0x0000 + 0 SET_REG1 A = 0x0F B = A ---------------- REG 0x000F = A SET_REG1 B = 0x0F DE = DE - 1 ---------------- REG 0x002D = DE SUB2 0x002C = 0x002D - 0x0001 SET_REG2 DE = 0x002C goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x002C = E SUB1 0xD4 = 0x00 - 0x2C flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002C = E TEST_BIT 0 = bool(0x002C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002C = E TEST_BIT 0 = bool(0x002C & 0x0080) REG 0x0000 = A REG 0x002C = E SUB1 0xD4 = 0x00 - 0x2C TEST_BIT 1 = bool(0x00D4 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x002C = E SUB1 0xD4 = 0x00 - 0x2C TEST_BIT 1 = bool(0x00D4 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00DC = C SET_REG1 A = 0xDC temp1.b = A ---------------- REG 0x00DC = A SET_REG1 temp1 = 0xDC A = A + E ---------------- REG 0x00DC = A REG 0x002C = E ADD1 0x08 = 0xDC + 0x2C SET_REG1 A = 0x08 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00DC = temp1 REG 0x002C = E SUB1 0xD3 = 0xFF - 0x2C CMP_UGT 1 = 0x00DC > 0x00D3 SET_FLAG c = 1 C = A ---------------- REG 0x0008 = A SET_REG1 C = 0x08 A = B ---------------- REG 0x000F = B SET_REG1 A = 0x0F A = adc.b(A, D, flag:c) ---------------- REG 0x000F = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0010 = 0x000F + 0x0000 + 1 SET_REG1 A = 0x10 B = A ---------------- REG 0x0010 = A SET_REG1 B = 0x10 DE = DE - 1 ---------------- REG 0x002C = DE SUB2 0x002B = 0x002C - 0x0001 SET_REG2 DE = 0x002B goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x002B = E SUB1 0xD5 = 0x00 - 0x2B flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002B = E TEST_BIT 0 = bool(0x002B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002B = E TEST_BIT 0 = bool(0x002B & 0x0080) REG 0x0000 = A REG 0x002B = E SUB1 0xD5 = 0x00 - 0x2B TEST_BIT 1 = bool(0x00D5 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x002B = E SUB1 0xD5 = 0x00 - 0x2B TEST_BIT 1 = bool(0x00D5 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0008 = C SET_REG1 A = 0x08 temp1.b = A ---------------- REG 0x0008 = A SET_REG1 temp1 = 0x08 A = A + E ---------------- REG 0x0008 = A REG 0x002B = E ADD1 0x33 = 0x08 + 0x2B SET_REG1 A = 0x33 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0008 = temp1 REG 0x002B = E SUB1 0xD4 = 0xFF - 0x2B CMP_UGT 0 = 0x0008 > 0x00D4 SET_FLAG c = 0 C = A ---------------- REG 0x0033 = A SET_REG1 C = 0x33 A = B ---------------- REG 0x0010 = B SET_REG1 A = 0x10 A = adc.b(A, D, flag:c) ---------------- REG 0x0010 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0010 = 0x0010 + 0x0000 + 0 SET_REG1 A = 0x10 B = A ---------------- REG 0x0010 = A SET_REG1 B = 0x10 DE = DE - 1 ---------------- REG 0x002B = DE SUB2 0x002A = 0x002B - 0x0001 SET_REG2 DE = 0x002A goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x002A = E SUB1 0xD6 = 0x00 - 0x2A flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x002A = E TEST_BIT 0 = bool(0x002A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x002A = E TEST_BIT 0 = bool(0x002A & 0x0080) REG 0x0000 = A REG 0x002A = E SUB1 0xD6 = 0x00 - 0x2A TEST_BIT 1 = bool(0x00D6 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x002A = E SUB1 0xD6 = 0x00 - 0x2A TEST_BIT 1 = bool(0x00D6 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0033 = C SET_REG1 A = 0x33 temp1.b = A ---------------- REG 0x0033 = A SET_REG1 temp1 = 0x33 A = A + E ---------------- REG 0x0033 = A REG 0x002A = E ADD1 0x5D = 0x33 + 0x2A SET_REG1 A = 0x5D flag:c = temp1.b u> 0xff - E ---------------- REG 0x0033 = temp1 REG 0x002A = E SUB1 0xD5 = 0xFF - 0x2A CMP_UGT 0 = 0x0033 > 0x00D5 SET_FLAG c = 0 C = A ---------------- REG 0x005D = A SET_REG1 C = 0x5D A = B ---------------- REG 0x0010 = B SET_REG1 A = 0x10 A = adc.b(A, D, flag:c) ---------------- REG 0x0010 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0010 = 0x0010 + 0x0000 + 0 SET_REG1 A = 0x10 B = A ---------------- REG 0x0010 = A SET_REG1 B = 0x10 DE = DE - 1 ---------------- REG 0x002A = DE SUB2 0x0029 = 0x002A - 0x0001 SET_REG2 DE = 0x0029 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0029 = E SUB1 0xD7 = 0x00 - 0x29 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0029 = E TEST_BIT 0 = bool(0x0029 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0029 = E TEST_BIT 0 = bool(0x0029 & 0x0080) REG 0x0000 = A REG 0x0029 = E SUB1 0xD7 = 0x00 - 0x29 TEST_BIT 1 = bool(0x00D7 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0029 = E SUB1 0xD7 = 0x00 - 0x29 TEST_BIT 1 = bool(0x00D7 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x005D = C SET_REG1 A = 0x5D temp1.b = A ---------------- REG 0x005D = A SET_REG1 temp1 = 0x5D A = A + E ---------------- REG 0x005D = A REG 0x0029 = E ADD1 0x86 = 0x5D + 0x29 SET_REG1 A = 0x86 flag:c = temp1.b u> 0xff - E ---------------- REG 0x005D = temp1 REG 0x0029 = E SUB1 0xD6 = 0xFF - 0x29 CMP_UGT 0 = 0x005D > 0x00D6 SET_FLAG c = 0 C = A ---------------- REG 0x0086 = A SET_REG1 C = 0x86 A = B ---------------- REG 0x0010 = B SET_REG1 A = 0x10 A = adc.b(A, D, flag:c) ---------------- REG 0x0010 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0010 = 0x0010 + 0x0000 + 0 SET_REG1 A = 0x10 B = A ---------------- REG 0x0010 = A SET_REG1 B = 0x10 DE = DE - 1 ---------------- REG 0x0029 = DE SUB2 0x0028 = 0x0029 - 0x0001 SET_REG2 DE = 0x0028 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0028 = E SUB1 0xD8 = 0x00 - 0x28 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0028 = E TEST_BIT 0 = bool(0x0028 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0028 = E TEST_BIT 0 = bool(0x0028 & 0x0080) REG 0x0000 = A REG 0x0028 = E SUB1 0xD8 = 0x00 - 0x28 TEST_BIT 1 = bool(0x00D8 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0028 = E SUB1 0xD8 = 0x00 - 0x28 TEST_BIT 1 = bool(0x00D8 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0086 = C SET_REG1 A = 0x86 temp1.b = A ---------------- REG 0x0086 = A SET_REG1 temp1 = 0x86 A = A + E ---------------- REG 0x0086 = A REG 0x0028 = E ADD1 0xAE = 0x86 + 0x28 SET_REG1 A = 0xAE flag:c = temp1.b u> 0xff - E ---------------- REG 0x0086 = temp1 REG 0x0028 = E SUB1 0xD7 = 0xFF - 0x28 CMP_UGT 0 = 0x0086 > 0x00D7 SET_FLAG c = 0 C = A ---------------- REG 0x00AE = A SET_REG1 C = 0xAE A = B ---------------- REG 0x0010 = B SET_REG1 A = 0x10 A = adc.b(A, D, flag:c) ---------------- REG 0x0010 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0010 = 0x0010 + 0x0000 + 0 SET_REG1 A = 0x10 B = A ---------------- REG 0x0010 = A SET_REG1 B = 0x10 DE = DE - 1 ---------------- REG 0x0028 = DE SUB2 0x0027 = 0x0028 - 0x0001 SET_REG2 DE = 0x0027 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0027 = E SUB1 0xD9 = 0x00 - 0x27 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0027 = E TEST_BIT 0 = bool(0x0027 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0027 = E TEST_BIT 0 = bool(0x0027 & 0x0080) REG 0x0000 = A REG 0x0027 = E SUB1 0xD9 = 0x00 - 0x27 TEST_BIT 1 = bool(0x00D9 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0027 = E SUB1 0xD9 = 0x00 - 0x27 TEST_BIT 1 = bool(0x00D9 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00AE = C SET_REG1 A = 0xAE temp1.b = A ---------------- REG 0x00AE = A SET_REG1 temp1 = 0xAE A = A + E ---------------- REG 0x00AE = A REG 0x0027 = E ADD1 0xD5 = 0xAE + 0x27 SET_REG1 A = 0xD5 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00AE = temp1 REG 0x0027 = E SUB1 0xD8 = 0xFF - 0x27 CMP_UGT 0 = 0x00AE > 0x00D8 SET_FLAG c = 0 C = A ---------------- REG 0x00D5 = A SET_REG1 C = 0xD5 A = B ---------------- REG 0x0010 = B SET_REG1 A = 0x10 A = adc.b(A, D, flag:c) ---------------- REG 0x0010 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0010 = 0x0010 + 0x0000 + 0 SET_REG1 A = 0x10 B = A ---------------- REG 0x0010 = A SET_REG1 B = 0x10 DE = DE - 1 ---------------- REG 0x0027 = DE SUB2 0x0026 = 0x0027 - 0x0001 SET_REG2 DE = 0x0026 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0026 = E SUB1 0xDA = 0x00 - 0x26 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0026 = E TEST_BIT 0 = bool(0x0026 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0026 = E TEST_BIT 0 = bool(0x0026 & 0x0080) REG 0x0000 = A REG 0x0026 = E SUB1 0xDA = 0x00 - 0x26 TEST_BIT 1 = bool(0x00DA & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0026 = E SUB1 0xDA = 0x00 - 0x26 TEST_BIT 1 = bool(0x00DA & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00D5 = C SET_REG1 A = 0xD5 temp1.b = A ---------------- REG 0x00D5 = A SET_REG1 temp1 = 0xD5 A = A + E ---------------- REG 0x00D5 = A REG 0x0026 = E ADD1 0xFB = 0xD5 + 0x26 SET_REG1 A = 0xFB flag:c = temp1.b u> 0xff - E ---------------- REG 0x00D5 = temp1 REG 0x0026 = E SUB1 0xD9 = 0xFF - 0x26 CMP_UGT 0 = 0x00D5 > 0x00D9 SET_FLAG c = 0 C = A ---------------- REG 0x00FB = A SET_REG1 C = 0xFB A = B ---------------- REG 0x0010 = B SET_REG1 A = 0x10 A = adc.b(A, D, flag:c) ---------------- REG 0x0010 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0010 = 0x0010 + 0x0000 + 0 SET_REG1 A = 0x10 B = A ---------------- REG 0x0010 = A SET_REG1 B = 0x10 DE = DE - 1 ---------------- REG 0x0026 = DE SUB2 0x0025 = 0x0026 - 0x0001 SET_REG2 DE = 0x0025 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0025 = E SUB1 0xDB = 0x00 - 0x25 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0025 = E TEST_BIT 0 = bool(0x0025 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0025 = E TEST_BIT 0 = bool(0x0025 & 0x0080) REG 0x0000 = A REG 0x0025 = E SUB1 0xDB = 0x00 - 0x25 TEST_BIT 1 = bool(0x00DB & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0025 = E SUB1 0xDB = 0x00 - 0x25 TEST_BIT 1 = bool(0x00DB & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00FB = C SET_REG1 A = 0xFB temp1.b = A ---------------- REG 0x00FB = A SET_REG1 temp1 = 0xFB A = A + E ---------------- REG 0x00FB = A REG 0x0025 = E ADD1 0x20 = 0xFB + 0x25 SET_REG1 A = 0x20 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00FB = temp1 REG 0x0025 = E SUB1 0xDA = 0xFF - 0x25 CMP_UGT 1 = 0x00FB > 0x00DA SET_FLAG c = 1 C = A ---------------- REG 0x0020 = A SET_REG1 C = 0x20 A = B ---------------- REG 0x0010 = B SET_REG1 A = 0x10 A = adc.b(A, D, flag:c) ---------------- REG 0x0010 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0011 = 0x0010 + 0x0000 + 1 SET_REG1 A = 0x11 B = A ---------------- REG 0x0011 = A SET_REG1 B = 0x11 DE = DE - 1 ---------------- REG 0x0025 = DE SUB2 0x0024 = 0x0025 - 0x0001 SET_REG2 DE = 0x0024 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0024 = E SUB1 0xDC = 0x00 - 0x24 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0024 = E TEST_BIT 0 = bool(0x0024 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0024 = E TEST_BIT 0 = bool(0x0024 & 0x0080) REG 0x0000 = A REG 0x0024 = E SUB1 0xDC = 0x00 - 0x24 TEST_BIT 1 = bool(0x00DC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0024 = E SUB1 0xDC = 0x00 - 0x24 TEST_BIT 1 = bool(0x00DC & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0020 = C SET_REG1 A = 0x20 temp1.b = A ---------------- REG 0x0020 = A SET_REG1 temp1 = 0x20 A = A + E ---------------- REG 0x0020 = A REG 0x0024 = E ADD1 0x44 = 0x20 + 0x24 SET_REG1 A = 0x44 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0020 = temp1 REG 0x0024 = E SUB1 0xDB = 0xFF - 0x24 CMP_UGT 0 = 0x0020 > 0x00DB SET_FLAG c = 0 C = A ---------------- REG 0x0044 = A SET_REG1 C = 0x44 A = B ---------------- REG 0x0011 = B SET_REG1 A = 0x11 A = adc.b(A, D, flag:c) ---------------- REG 0x0011 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0011 = 0x0011 + 0x0000 + 0 SET_REG1 A = 0x11 B = A ---------------- REG 0x0011 = A SET_REG1 B = 0x11 DE = DE - 1 ---------------- REG 0x0024 = DE SUB2 0x0023 = 0x0024 - 0x0001 SET_REG2 DE = 0x0023 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0023 = E SUB1 0xDD = 0x00 - 0x23 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0023 = E TEST_BIT 0 = bool(0x0023 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0023 = E TEST_BIT 0 = bool(0x0023 & 0x0080) REG 0x0000 = A REG 0x0023 = E SUB1 0xDD = 0x00 - 0x23 TEST_BIT 1 = bool(0x00DD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0023 = E SUB1 0xDD = 0x00 - 0x23 TEST_BIT 1 = bool(0x00DD & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0044 = C SET_REG1 A = 0x44 temp1.b = A ---------------- REG 0x0044 = A SET_REG1 temp1 = 0x44 A = A + E ---------------- REG 0x0044 = A REG 0x0023 = E ADD1 0x67 = 0x44 + 0x23 SET_REG1 A = 0x67 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0044 = temp1 REG 0x0023 = E SUB1 0xDC = 0xFF - 0x23 CMP_UGT 0 = 0x0044 > 0x00DC SET_FLAG c = 0 C = A ---------------- REG 0x0067 = A SET_REG1 C = 0x67 A = B ---------------- REG 0x0011 = B SET_REG1 A = 0x11 A = adc.b(A, D, flag:c) ---------------- REG 0x0011 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0011 = 0x0011 + 0x0000 + 0 SET_REG1 A = 0x11 B = A ---------------- REG 0x0011 = A SET_REG1 B = 0x11 DE = DE - 1 ---------------- REG 0x0023 = DE SUB2 0x0022 = 0x0023 - 0x0001 SET_REG2 DE = 0x0022 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0022 = E SUB1 0xDE = 0x00 - 0x22 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0022 = E TEST_BIT 0 = bool(0x0022 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0022 = E TEST_BIT 0 = bool(0x0022 & 0x0080) REG 0x0000 = A REG 0x0022 = E SUB1 0xDE = 0x00 - 0x22 TEST_BIT 1 = bool(0x00DE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0022 = E SUB1 0xDE = 0x00 - 0x22 TEST_BIT 1 = bool(0x00DE & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0067 = C SET_REG1 A = 0x67 temp1.b = A ---------------- REG 0x0067 = A SET_REG1 temp1 = 0x67 A = A + E ---------------- REG 0x0067 = A REG 0x0022 = E ADD1 0x89 = 0x67 + 0x22 SET_REG1 A = 0x89 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0067 = temp1 REG 0x0022 = E SUB1 0xDD = 0xFF - 0x22 CMP_UGT 0 = 0x0067 > 0x00DD SET_FLAG c = 0 C = A ---------------- REG 0x0089 = A SET_REG1 C = 0x89 A = B ---------------- REG 0x0011 = B SET_REG1 A = 0x11 A = adc.b(A, D, flag:c) ---------------- REG 0x0011 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0011 = 0x0011 + 0x0000 + 0 SET_REG1 A = 0x11 B = A ---------------- REG 0x0011 = A SET_REG1 B = 0x11 DE = DE - 1 ---------------- REG 0x0022 = DE SUB2 0x0021 = 0x0022 - 0x0001 SET_REG2 DE = 0x0021 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0021 = E SUB1 0xDF = 0x00 - 0x21 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0021 = E TEST_BIT 0 = bool(0x0021 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0021 = E TEST_BIT 0 = bool(0x0021 & 0x0080) REG 0x0000 = A REG 0x0021 = E SUB1 0xDF = 0x00 - 0x21 TEST_BIT 1 = bool(0x00DF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0021 = E SUB1 0xDF = 0x00 - 0x21 TEST_BIT 1 = bool(0x00DF & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0089 = C SET_REG1 A = 0x89 temp1.b = A ---------------- REG 0x0089 = A SET_REG1 temp1 = 0x89 A = A + E ---------------- REG 0x0089 = A REG 0x0021 = E ADD1 0xAA = 0x89 + 0x21 SET_REG1 A = 0xAA flag:c = temp1.b u> 0xff - E ---------------- REG 0x0089 = temp1 REG 0x0021 = E SUB1 0xDE = 0xFF - 0x21 CMP_UGT 0 = 0x0089 > 0x00DE SET_FLAG c = 0 C = A ---------------- REG 0x00AA = A SET_REG1 C = 0xAA A = B ---------------- REG 0x0011 = B SET_REG1 A = 0x11 A = adc.b(A, D, flag:c) ---------------- REG 0x0011 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0011 = 0x0011 + 0x0000 + 0 SET_REG1 A = 0x11 B = A ---------------- REG 0x0011 = A SET_REG1 B = 0x11 DE = DE - 1 ---------------- REG 0x0021 = DE SUB2 0x0020 = 0x0021 - 0x0001 SET_REG2 DE = 0x0020 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0020 = E SUB1 0xE0 = 0x00 - 0x20 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0020 = E TEST_BIT 0 = bool(0x0020 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0020 = E TEST_BIT 0 = bool(0x0020 & 0x0080) REG 0x0000 = A REG 0x0020 = E SUB1 0xE0 = 0x00 - 0x20 TEST_BIT 1 = bool(0x00E0 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0020 = E SUB1 0xE0 = 0x00 - 0x20 TEST_BIT 1 = bool(0x00E0 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00AA = C SET_REG1 A = 0xAA temp1.b = A ---------------- REG 0x00AA = A SET_REG1 temp1 = 0xAA A = A + E ---------------- REG 0x00AA = A REG 0x0020 = E ADD1 0xCA = 0xAA + 0x20 SET_REG1 A = 0xCA flag:c = temp1.b u> 0xff - E ---------------- REG 0x00AA = temp1 REG 0x0020 = E SUB1 0xDF = 0xFF - 0x20 CMP_UGT 0 = 0x00AA > 0x00DF SET_FLAG c = 0 C = A ---------------- REG 0x00CA = A SET_REG1 C = 0xCA A = B ---------------- REG 0x0011 = B SET_REG1 A = 0x11 A = adc.b(A, D, flag:c) ---------------- REG 0x0011 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0011 = 0x0011 + 0x0000 + 0 SET_REG1 A = 0x11 B = A ---------------- REG 0x0011 = A SET_REG1 B = 0x11 DE = DE - 1 ---------------- REG 0x0020 = DE SUB2 0x001F = 0x0020 - 0x0001 SET_REG2 DE = 0x001F goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x001F = E SUB1 0xE1 = 0x00 - 0x1F flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001F = E TEST_BIT 0 = bool(0x001F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001F = E TEST_BIT 0 = bool(0x001F & 0x0080) REG 0x0000 = A REG 0x001F = E SUB1 0xE1 = 0x00 - 0x1F TEST_BIT 1 = bool(0x00E1 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x001F = E SUB1 0xE1 = 0x00 - 0x1F TEST_BIT 1 = bool(0x00E1 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00CA = C SET_REG1 A = 0xCA temp1.b = A ---------------- REG 0x00CA = A SET_REG1 temp1 = 0xCA A = A + E ---------------- REG 0x00CA = A REG 0x001F = E ADD1 0xE9 = 0xCA + 0x1F SET_REG1 A = 0xE9 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00CA = temp1 REG 0x001F = E SUB1 0xE0 = 0xFF - 0x1F CMP_UGT 0 = 0x00CA > 0x00E0 SET_FLAG c = 0 C = A ---------------- REG 0x00E9 = A SET_REG1 C = 0xE9 A = B ---------------- REG 0x0011 = B SET_REG1 A = 0x11 A = adc.b(A, D, flag:c) ---------------- REG 0x0011 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0011 = 0x0011 + 0x0000 + 0 SET_REG1 A = 0x11 B = A ---------------- REG 0x0011 = A SET_REG1 B = 0x11 DE = DE - 1 ---------------- REG 0x001F = DE SUB2 0x001E = 0x001F - 0x0001 SET_REG2 DE = 0x001E goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x001E = E SUB1 0xE2 = 0x00 - 0x1E flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001E = E TEST_BIT 0 = bool(0x001E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001E = E TEST_BIT 0 = bool(0x001E & 0x0080) REG 0x0000 = A REG 0x001E = E SUB1 0xE2 = 0x00 - 0x1E TEST_BIT 1 = bool(0x00E2 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x001E = E SUB1 0xE2 = 0x00 - 0x1E TEST_BIT 1 = bool(0x00E2 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00E9 = C SET_REG1 A = 0xE9 temp1.b = A ---------------- REG 0x00E9 = A SET_REG1 temp1 = 0xE9 A = A + E ---------------- REG 0x00E9 = A REG 0x001E = E ADD1 0x07 = 0xE9 + 0x1E SET_REG1 A = 0x07 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00E9 = temp1 REG 0x001E = E SUB1 0xE1 = 0xFF - 0x1E CMP_UGT 1 = 0x00E9 > 0x00E1 SET_FLAG c = 1 C = A ---------------- REG 0x0007 = A SET_REG1 C = 0x07 A = B ---------------- REG 0x0011 = B SET_REG1 A = 0x11 A = adc.b(A, D, flag:c) ---------------- REG 0x0011 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0012 = 0x0011 + 0x0000 + 1 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x001E = DE SUB2 0x001D = 0x001E - 0x0001 SET_REG2 DE = 0x001D goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x001D = E SUB1 0xE3 = 0x00 - 0x1D flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001D = E TEST_BIT 0 = bool(0x001D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001D = E TEST_BIT 0 = bool(0x001D & 0x0080) REG 0x0000 = A REG 0x001D = E SUB1 0xE3 = 0x00 - 0x1D TEST_BIT 1 = bool(0x00E3 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x001D = E SUB1 0xE3 = 0x00 - 0x1D TEST_BIT 1 = bool(0x00E3 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0007 = C SET_REG1 A = 0x07 temp1.b = A ---------------- REG 0x0007 = A SET_REG1 temp1 = 0x07 A = A + E ---------------- REG 0x0007 = A REG 0x001D = E ADD1 0x24 = 0x07 + 0x1D SET_REG1 A = 0x24 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0007 = temp1 REG 0x001D = E SUB1 0xE2 = 0xFF - 0x1D CMP_UGT 0 = 0x0007 > 0x00E2 SET_FLAG c = 0 C = A ---------------- REG 0x0024 = A SET_REG1 C = 0x24 A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x001D = DE SUB2 0x001C = 0x001D - 0x0001 SET_REG2 DE = 0x001C goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x001C = E SUB1 0xE4 = 0x00 - 0x1C flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001C = E TEST_BIT 0 = bool(0x001C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001C = E TEST_BIT 0 = bool(0x001C & 0x0080) REG 0x0000 = A REG 0x001C = E SUB1 0xE4 = 0x00 - 0x1C TEST_BIT 1 = bool(0x00E4 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x001C = E SUB1 0xE4 = 0x00 - 0x1C TEST_BIT 1 = bool(0x00E4 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0024 = C SET_REG1 A = 0x24 temp1.b = A ---------------- REG 0x0024 = A SET_REG1 temp1 = 0x24 A = A + E ---------------- REG 0x0024 = A REG 0x001C = E ADD1 0x40 = 0x24 + 0x1C SET_REG1 A = 0x40 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0024 = temp1 REG 0x001C = E SUB1 0xE3 = 0xFF - 0x1C CMP_UGT 0 = 0x0024 > 0x00E3 SET_FLAG c = 0 C = A ---------------- REG 0x0040 = A SET_REG1 C = 0x40 A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x001C = DE SUB2 0x001B = 0x001C - 0x0001 SET_REG2 DE = 0x001B goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x001B = E SUB1 0xE5 = 0x00 - 0x1B flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001B = E TEST_BIT 0 = bool(0x001B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001B = E TEST_BIT 0 = bool(0x001B & 0x0080) REG 0x0000 = A REG 0x001B = E SUB1 0xE5 = 0x00 - 0x1B TEST_BIT 1 = bool(0x00E5 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x001B = E SUB1 0xE5 = 0x00 - 0x1B TEST_BIT 1 = bool(0x00E5 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0040 = C SET_REG1 A = 0x40 temp1.b = A ---------------- REG 0x0040 = A SET_REG1 temp1 = 0x40 A = A + E ---------------- REG 0x0040 = A REG 0x001B = E ADD1 0x5B = 0x40 + 0x1B SET_REG1 A = 0x5B flag:c = temp1.b u> 0xff - E ---------------- REG 0x0040 = temp1 REG 0x001B = E SUB1 0xE4 = 0xFF - 0x1B CMP_UGT 0 = 0x0040 > 0x00E4 SET_FLAG c = 0 C = A ---------------- REG 0x005B = A SET_REG1 C = 0x5B A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x001B = DE SUB2 0x001A = 0x001B - 0x0001 SET_REG2 DE = 0x001A goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x001A = E SUB1 0xE6 = 0x00 - 0x1A flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x001A = E TEST_BIT 0 = bool(0x001A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x001A = E TEST_BIT 0 = bool(0x001A & 0x0080) REG 0x0000 = A REG 0x001A = E SUB1 0xE6 = 0x00 - 0x1A TEST_BIT 1 = bool(0x00E6 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x001A = E SUB1 0xE6 = 0x00 - 0x1A TEST_BIT 1 = bool(0x00E6 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x005B = C SET_REG1 A = 0x5B temp1.b = A ---------------- REG 0x005B = A SET_REG1 temp1 = 0x5B A = A + E ---------------- REG 0x005B = A REG 0x001A = E ADD1 0x75 = 0x5B + 0x1A SET_REG1 A = 0x75 flag:c = temp1.b u> 0xff - E ---------------- REG 0x005B = temp1 REG 0x001A = E SUB1 0xE5 = 0xFF - 0x1A CMP_UGT 0 = 0x005B > 0x00E5 SET_FLAG c = 0 C = A ---------------- REG 0x0075 = A SET_REG1 C = 0x75 A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x001A = DE SUB2 0x0019 = 0x001A - 0x0001 SET_REG2 DE = 0x0019 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0019 = E SUB1 0xE7 = 0x00 - 0x19 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0019 = E TEST_BIT 0 = bool(0x0019 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0019 = E TEST_BIT 0 = bool(0x0019 & 0x0080) REG 0x0000 = A REG 0x0019 = E SUB1 0xE7 = 0x00 - 0x19 TEST_BIT 1 = bool(0x00E7 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0019 = E SUB1 0xE7 = 0x00 - 0x19 TEST_BIT 1 = bool(0x00E7 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0075 = C SET_REG1 A = 0x75 temp1.b = A ---------------- REG 0x0075 = A SET_REG1 temp1 = 0x75 A = A + E ---------------- REG 0x0075 = A REG 0x0019 = E ADD1 0x8E = 0x75 + 0x19 SET_REG1 A = 0x8E flag:c = temp1.b u> 0xff - E ---------------- REG 0x0075 = temp1 REG 0x0019 = E SUB1 0xE6 = 0xFF - 0x19 CMP_UGT 0 = 0x0075 > 0x00E6 SET_FLAG c = 0 C = A ---------------- REG 0x008E = A SET_REG1 C = 0x8E A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x0019 = DE SUB2 0x0018 = 0x0019 - 0x0001 SET_REG2 DE = 0x0018 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0018 = E SUB1 0xE8 = 0x00 - 0x18 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0018 = E TEST_BIT 0 = bool(0x0018 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0018 = E TEST_BIT 0 = bool(0x0018 & 0x0080) REG 0x0000 = A REG 0x0018 = E SUB1 0xE8 = 0x00 - 0x18 TEST_BIT 1 = bool(0x00E8 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0018 = E SUB1 0xE8 = 0x00 - 0x18 TEST_BIT 1 = bool(0x00E8 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x008E = C SET_REG1 A = 0x8E temp1.b = A ---------------- REG 0x008E = A SET_REG1 temp1 = 0x8E A = A + E ---------------- REG 0x008E = A REG 0x0018 = E ADD1 0xA6 = 0x8E + 0x18 SET_REG1 A = 0xA6 flag:c = temp1.b u> 0xff - E ---------------- REG 0x008E = temp1 REG 0x0018 = E SUB1 0xE7 = 0xFF - 0x18 CMP_UGT 0 = 0x008E > 0x00E7 SET_FLAG c = 0 C = A ---------------- REG 0x00A6 = A SET_REG1 C = 0xA6 A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x0018 = DE SUB2 0x0017 = 0x0018 - 0x0001 SET_REG2 DE = 0x0017 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0017 = E SUB1 0xE9 = 0x00 - 0x17 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0017 = E TEST_BIT 0 = bool(0x0017 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0017 = E TEST_BIT 0 = bool(0x0017 & 0x0080) REG 0x0000 = A REG 0x0017 = E SUB1 0xE9 = 0x00 - 0x17 TEST_BIT 1 = bool(0x00E9 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0017 = E SUB1 0xE9 = 0x00 - 0x17 TEST_BIT 1 = bool(0x00E9 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00A6 = C SET_REG1 A = 0xA6 temp1.b = A ---------------- REG 0x00A6 = A SET_REG1 temp1 = 0xA6 A = A + E ---------------- REG 0x00A6 = A REG 0x0017 = E ADD1 0xBD = 0xA6 + 0x17 SET_REG1 A = 0xBD flag:c = temp1.b u> 0xff - E ---------------- REG 0x00A6 = temp1 REG 0x0017 = E SUB1 0xE8 = 0xFF - 0x17 CMP_UGT 0 = 0x00A6 > 0x00E8 SET_FLAG c = 0 C = A ---------------- REG 0x00BD = A SET_REG1 C = 0xBD A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x0017 = DE SUB2 0x0016 = 0x0017 - 0x0001 SET_REG2 DE = 0x0016 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0016 = E SUB1 0xEA = 0x00 - 0x16 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0016 = E TEST_BIT 0 = bool(0x0016 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0016 = E TEST_BIT 0 = bool(0x0016 & 0x0080) REG 0x0000 = A REG 0x0016 = E SUB1 0xEA = 0x00 - 0x16 TEST_BIT 1 = bool(0x00EA & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0016 = E SUB1 0xEA = 0x00 - 0x16 TEST_BIT 1 = bool(0x00EA & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00BD = C SET_REG1 A = 0xBD temp1.b = A ---------------- REG 0x00BD = A SET_REG1 temp1 = 0xBD A = A + E ---------------- REG 0x00BD = A REG 0x0016 = E ADD1 0xD3 = 0xBD + 0x16 SET_REG1 A = 0xD3 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00BD = temp1 REG 0x0016 = E SUB1 0xE9 = 0xFF - 0x16 CMP_UGT 0 = 0x00BD > 0x00E9 SET_FLAG c = 0 C = A ---------------- REG 0x00D3 = A SET_REG1 C = 0xD3 A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x0016 = DE SUB2 0x0015 = 0x0016 - 0x0001 SET_REG2 DE = 0x0015 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0015 = E SUB1 0xEB = 0x00 - 0x15 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0015 = E TEST_BIT 0 = bool(0x0015 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0015 = E TEST_BIT 0 = bool(0x0015 & 0x0080) REG 0x0000 = A REG 0x0015 = E SUB1 0xEB = 0x00 - 0x15 TEST_BIT 1 = bool(0x00EB & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0015 = E SUB1 0xEB = 0x00 - 0x15 TEST_BIT 1 = bool(0x00EB & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00D3 = C SET_REG1 A = 0xD3 temp1.b = A ---------------- REG 0x00D3 = A SET_REG1 temp1 = 0xD3 A = A + E ---------------- REG 0x00D3 = A REG 0x0015 = E ADD1 0xE8 = 0xD3 + 0x15 SET_REG1 A = 0xE8 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00D3 = temp1 REG 0x0015 = E SUB1 0xEA = 0xFF - 0x15 CMP_UGT 0 = 0x00D3 > 0x00EA SET_FLAG c = 0 C = A ---------------- REG 0x00E8 = A SET_REG1 C = 0xE8 A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x0015 = DE SUB2 0x0014 = 0x0015 - 0x0001 SET_REG2 DE = 0x0014 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0014 = E SUB1 0xEC = 0x00 - 0x14 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0014 = E TEST_BIT 0 = bool(0x0014 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0014 = E TEST_BIT 0 = bool(0x0014 & 0x0080) REG 0x0000 = A REG 0x0014 = E SUB1 0xEC = 0x00 - 0x14 TEST_BIT 1 = bool(0x00EC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0014 = E SUB1 0xEC = 0x00 - 0x14 TEST_BIT 1 = bool(0x00EC & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00E8 = C SET_REG1 A = 0xE8 temp1.b = A ---------------- REG 0x00E8 = A SET_REG1 temp1 = 0xE8 A = A + E ---------------- REG 0x00E8 = A REG 0x0014 = E ADD1 0xFC = 0xE8 + 0x14 SET_REG1 A = 0xFC flag:c = temp1.b u> 0xff - E ---------------- REG 0x00E8 = temp1 REG 0x0014 = E SUB1 0xEB = 0xFF - 0x14 CMP_UGT 0 = 0x00E8 > 0x00EB SET_FLAG c = 0 C = A ---------------- REG 0x00FC = A SET_REG1 C = 0xFC A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0012 = 0x0012 + 0x0000 + 0 SET_REG1 A = 0x12 B = A ---------------- REG 0x0012 = A SET_REG1 B = 0x12 DE = DE - 1 ---------------- REG 0x0014 = DE SUB2 0x0013 = 0x0014 - 0x0001 SET_REG2 DE = 0x0013 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0013 = E SUB1 0xED = 0x00 - 0x13 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0013 = E TEST_BIT 0 = bool(0x0013 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0013 = E TEST_BIT 0 = bool(0x0013 & 0x0080) REG 0x0000 = A REG 0x0013 = E SUB1 0xED = 0x00 - 0x13 TEST_BIT 1 = bool(0x00ED & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0013 = E SUB1 0xED = 0x00 - 0x13 TEST_BIT 1 = bool(0x00ED & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00FC = C SET_REG1 A = 0xFC temp1.b = A ---------------- REG 0x00FC = A SET_REG1 temp1 = 0xFC A = A + E ---------------- REG 0x00FC = A REG 0x0013 = E ADD1 0x0F = 0xFC + 0x13 SET_REG1 A = 0x0F flag:c = temp1.b u> 0xff - E ---------------- REG 0x00FC = temp1 REG 0x0013 = E SUB1 0xEC = 0xFF - 0x13 CMP_UGT 1 = 0x00FC > 0x00EC SET_FLAG c = 1 C = A ---------------- REG 0x000F = A SET_REG1 C = 0x0F A = B ---------------- REG 0x0012 = B SET_REG1 A = 0x12 A = adc.b(A, D, flag:c) ---------------- REG 0x0012 = A REG 0x0000 = D FLAG 1 = vm_flags[c] ADC 0x0013 = 0x0012 + 0x0000 + 1 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0013 = DE SUB2 0x0012 = 0x0013 - 0x0001 SET_REG2 DE = 0x0012 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0012 = E SUB1 0xEE = 0x00 - 0x12 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0012 = E TEST_BIT 0 = bool(0x0012 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0012 = E TEST_BIT 0 = bool(0x0012 & 0x0080) REG 0x0000 = A REG 0x0012 = E SUB1 0xEE = 0x00 - 0x12 TEST_BIT 1 = bool(0x00EE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0012 = E SUB1 0xEE = 0x00 - 0x12 TEST_BIT 1 = bool(0x00EE & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x000F = C SET_REG1 A = 0x0F temp1.b = A ---------------- REG 0x000F = A SET_REG1 temp1 = 0x0F A = A + E ---------------- REG 0x000F = A REG 0x0012 = E ADD1 0x21 = 0x0F + 0x12 SET_REG1 A = 0x21 flag:c = temp1.b u> 0xff - E ---------------- REG 0x000F = temp1 REG 0x0012 = E SUB1 0xED = 0xFF - 0x12 CMP_UGT 0 = 0x000F > 0x00ED SET_FLAG c = 0 C = A ---------------- REG 0x0021 = A SET_REG1 C = 0x21 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0012 = DE SUB2 0x0011 = 0x0012 - 0x0001 SET_REG2 DE = 0x0011 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0011 = E SUB1 0xEF = 0x00 - 0x11 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0011 = E TEST_BIT 0 = bool(0x0011 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0011 = E TEST_BIT 0 = bool(0x0011 & 0x0080) REG 0x0000 = A REG 0x0011 = E SUB1 0xEF = 0x00 - 0x11 TEST_BIT 1 = bool(0x00EF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0011 = E SUB1 0xEF = 0x00 - 0x11 TEST_BIT 1 = bool(0x00EF & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0021 = C SET_REG1 A = 0x21 temp1.b = A ---------------- REG 0x0021 = A SET_REG1 temp1 = 0x21 A = A + E ---------------- REG 0x0021 = A REG 0x0011 = E ADD1 0x32 = 0x21 + 0x11 SET_REG1 A = 0x32 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0021 = temp1 REG 0x0011 = E SUB1 0xEE = 0xFF - 0x11 CMP_UGT 0 = 0x0021 > 0x00EE SET_FLAG c = 0 C = A ---------------- REG 0x0032 = A SET_REG1 C = 0x32 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0011 = DE SUB2 0x0010 = 0x0011 - 0x0001 SET_REG2 DE = 0x0010 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0010 = E SUB1 0xF0 = 0x00 - 0x10 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0010 = E TEST_BIT 0 = bool(0x0010 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0010 = E TEST_BIT 0 = bool(0x0010 & 0x0080) REG 0x0000 = A REG 0x0010 = E SUB1 0xF0 = 0x00 - 0x10 TEST_BIT 1 = bool(0x00F0 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0010 = E SUB1 0xF0 = 0x00 - 0x10 TEST_BIT 1 = bool(0x00F0 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0032 = C SET_REG1 A = 0x32 temp1.b = A ---------------- REG 0x0032 = A SET_REG1 temp1 = 0x32 A = A + E ---------------- REG 0x0032 = A REG 0x0010 = E ADD1 0x42 = 0x32 + 0x10 SET_REG1 A = 0x42 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0032 = temp1 REG 0x0010 = E SUB1 0xEF = 0xFF - 0x10 CMP_UGT 0 = 0x0032 > 0x00EF SET_FLAG c = 0 C = A ---------------- REG 0x0042 = A SET_REG1 C = 0x42 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0010 = DE SUB2 0x000F = 0x0010 - 0x0001 SET_REG2 DE = 0x000F goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x000F = E SUB1 0xF1 = 0x00 - 0x0F flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000F = E TEST_BIT 0 = bool(0x000F & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000F = E TEST_BIT 0 = bool(0x000F & 0x0080) REG 0x0000 = A REG 0x000F = E SUB1 0xF1 = 0x00 - 0x0F TEST_BIT 1 = bool(0x00F1 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x000F = E SUB1 0xF1 = 0x00 - 0x0F TEST_BIT 1 = bool(0x00F1 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0042 = C SET_REG1 A = 0x42 temp1.b = A ---------------- REG 0x0042 = A SET_REG1 temp1 = 0x42 A = A + E ---------------- REG 0x0042 = A REG 0x000F = E ADD1 0x51 = 0x42 + 0x0F SET_REG1 A = 0x51 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0042 = temp1 REG 0x000F = E SUB1 0xF0 = 0xFF - 0x0F CMP_UGT 0 = 0x0042 > 0x00F0 SET_FLAG c = 0 C = A ---------------- REG 0x0051 = A SET_REG1 C = 0x51 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x000F = DE SUB2 0x000E = 0x000F - 0x0001 SET_REG2 DE = 0x000E goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x000E = E SUB1 0xF2 = 0x00 - 0x0E flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000E = E TEST_BIT 0 = bool(0x000E & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000E = E TEST_BIT 0 = bool(0x000E & 0x0080) REG 0x0000 = A REG 0x000E = E SUB1 0xF2 = 0x00 - 0x0E TEST_BIT 1 = bool(0x00F2 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x000E = E SUB1 0xF2 = 0x00 - 0x0E TEST_BIT 1 = bool(0x00F2 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0051 = C SET_REG1 A = 0x51 temp1.b = A ---------------- REG 0x0051 = A SET_REG1 temp1 = 0x51 A = A + E ---------------- REG 0x0051 = A REG 0x000E = E ADD1 0x5F = 0x51 + 0x0E SET_REG1 A = 0x5F flag:c = temp1.b u> 0xff - E ---------------- REG 0x0051 = temp1 REG 0x000E = E SUB1 0xF1 = 0xFF - 0x0E CMP_UGT 0 = 0x0051 > 0x00F1 SET_FLAG c = 0 C = A ---------------- REG 0x005F = A SET_REG1 C = 0x5F A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x000E = DE SUB2 0x000D = 0x000E - 0x0001 SET_REG2 DE = 0x000D goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x000D = E SUB1 0xF3 = 0x00 - 0x0D flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000D = E TEST_BIT 0 = bool(0x000D & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000D = E TEST_BIT 0 = bool(0x000D & 0x0080) REG 0x0000 = A REG 0x000D = E SUB1 0xF3 = 0x00 - 0x0D TEST_BIT 1 = bool(0x00F3 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x000D = E SUB1 0xF3 = 0x00 - 0x0D TEST_BIT 1 = bool(0x00F3 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x005F = C SET_REG1 A = 0x5F temp1.b = A ---------------- REG 0x005F = A SET_REG1 temp1 = 0x5F A = A + E ---------------- REG 0x005F = A REG 0x000D = E ADD1 0x6C = 0x5F + 0x0D SET_REG1 A = 0x6C flag:c = temp1.b u> 0xff - E ---------------- REG 0x005F = temp1 REG 0x000D = E SUB1 0xF2 = 0xFF - 0x0D CMP_UGT 0 = 0x005F > 0x00F2 SET_FLAG c = 0 C = A ---------------- REG 0x006C = A SET_REG1 C = 0x6C A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x000D = DE SUB2 0x000C = 0x000D - 0x0001 SET_REG2 DE = 0x000C goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x000C = E SUB1 0xF4 = 0x00 - 0x0C flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000C = E TEST_BIT 0 = bool(0x000C & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000C = E TEST_BIT 0 = bool(0x000C & 0x0080) REG 0x0000 = A REG 0x000C = E SUB1 0xF4 = 0x00 - 0x0C TEST_BIT 1 = bool(0x00F4 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x000C = E SUB1 0xF4 = 0x00 - 0x0C TEST_BIT 1 = bool(0x00F4 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x006C = C SET_REG1 A = 0x6C temp1.b = A ---------------- REG 0x006C = A SET_REG1 temp1 = 0x6C A = A + E ---------------- REG 0x006C = A REG 0x000C = E ADD1 0x78 = 0x6C + 0x0C SET_REG1 A = 0x78 flag:c = temp1.b u> 0xff - E ---------------- REG 0x006C = temp1 REG 0x000C = E SUB1 0xF3 = 0xFF - 0x0C CMP_UGT 0 = 0x006C > 0x00F3 SET_FLAG c = 0 C = A ---------------- REG 0x0078 = A SET_REG1 C = 0x78 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x000C = DE SUB2 0x000B = 0x000C - 0x0001 SET_REG2 DE = 0x000B goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x000B = E SUB1 0xF5 = 0x00 - 0x0B flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000B = E TEST_BIT 0 = bool(0x000B & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000B = E TEST_BIT 0 = bool(0x000B & 0x0080) REG 0x0000 = A REG 0x000B = E SUB1 0xF5 = 0x00 - 0x0B TEST_BIT 1 = bool(0x00F5 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x000B = E SUB1 0xF5 = 0x00 - 0x0B TEST_BIT 1 = bool(0x00F5 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0078 = C SET_REG1 A = 0x78 temp1.b = A ---------------- REG 0x0078 = A SET_REG1 temp1 = 0x78 A = A + E ---------------- REG 0x0078 = A REG 0x000B = E ADD1 0x83 = 0x78 + 0x0B SET_REG1 A = 0x83 flag:c = temp1.b u> 0xff - E ---------------- REG 0x0078 = temp1 REG 0x000B = E SUB1 0xF4 = 0xFF - 0x0B CMP_UGT 0 = 0x0078 > 0x00F4 SET_FLAG c = 0 C = A ---------------- REG 0x0083 = A SET_REG1 C = 0x83 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x000B = DE SUB2 0x000A = 0x000B - 0x0001 SET_REG2 DE = 0x000A goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x000A = E SUB1 0xF6 = 0x00 - 0x0A flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x000A = E TEST_BIT 0 = bool(0x000A & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x000A = E TEST_BIT 0 = bool(0x000A & 0x0080) REG 0x0000 = A REG 0x000A = E SUB1 0xF6 = 0x00 - 0x0A TEST_BIT 1 = bool(0x00F6 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x000A = E SUB1 0xF6 = 0x00 - 0x0A TEST_BIT 1 = bool(0x00F6 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0083 = C SET_REG1 A = 0x83 temp1.b = A ---------------- REG 0x0083 = A SET_REG1 temp1 = 0x83 A = A + E ---------------- REG 0x0083 = A REG 0x000A = E ADD1 0x8D = 0x83 + 0x0A SET_REG1 A = 0x8D flag:c = temp1.b u> 0xff - E ---------------- REG 0x0083 = temp1 REG 0x000A = E SUB1 0xF5 = 0xFF - 0x0A CMP_UGT 0 = 0x0083 > 0x00F5 SET_FLAG c = 0 C = A ---------------- REG 0x008D = A SET_REG1 C = 0x8D A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x000A = DE SUB2 0x0009 = 0x000A - 0x0001 SET_REG2 DE = 0x0009 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0009 = E SUB1 0xF7 = 0x00 - 0x09 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0009 = E TEST_BIT 0 = bool(0x0009 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0009 = E TEST_BIT 0 = bool(0x0009 & 0x0080) REG 0x0000 = A REG 0x0009 = E SUB1 0xF7 = 0x00 - 0x09 TEST_BIT 1 = bool(0x00F7 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0009 = E SUB1 0xF7 = 0x00 - 0x09 TEST_BIT 1 = bool(0x00F7 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x008D = C SET_REG1 A = 0x8D temp1.b = A ---------------- REG 0x008D = A SET_REG1 temp1 = 0x8D A = A + E ---------------- REG 0x008D = A REG 0x0009 = E ADD1 0x96 = 0x8D + 0x09 SET_REG1 A = 0x96 flag:c = temp1.b u> 0xff - E ---------------- REG 0x008D = temp1 REG 0x0009 = E SUB1 0xF6 = 0xFF - 0x09 CMP_UGT 0 = 0x008D > 0x00F6 SET_FLAG c = 0 C = A ---------------- REG 0x0096 = A SET_REG1 C = 0x96 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0009 = DE SUB2 0x0008 = 0x0009 - 0x0001 SET_REG2 DE = 0x0008 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0008 = E SUB1 0xF8 = 0x00 - 0x08 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0008 = E TEST_BIT 0 = bool(0x0008 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0008 = E TEST_BIT 0 = bool(0x0008 & 0x0080) REG 0x0000 = A REG 0x0008 = E SUB1 0xF8 = 0x00 - 0x08 TEST_BIT 1 = bool(0x00F8 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0008 = E SUB1 0xF8 = 0x00 - 0x08 TEST_BIT 1 = bool(0x00F8 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x0096 = C SET_REG1 A = 0x96 temp1.b = A ---------------- REG 0x0096 = A SET_REG1 temp1 = 0x96 A = A + E ---------------- REG 0x0096 = A REG 0x0008 = E ADD1 0x9E = 0x96 + 0x08 SET_REG1 A = 0x9E flag:c = temp1.b u> 0xff - E ---------------- REG 0x0096 = temp1 REG 0x0008 = E SUB1 0xF7 = 0xFF - 0x08 CMP_UGT 0 = 0x0096 > 0x00F7 SET_FLAG c = 0 C = A ---------------- REG 0x009E = A SET_REG1 C = 0x9E A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0008 = DE SUB2 0x0007 = 0x0008 - 0x0001 SET_REG2 DE = 0x0007 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0007 = E SUB1 0xF9 = 0x00 - 0x07 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0007 = E TEST_BIT 0 = bool(0x0007 & 0x0080) REG 0x0000 = A REG 0x0007 = E SUB1 0xF9 = 0x00 - 0x07 TEST_BIT 1 = bool(0x00F9 & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0007 = E SUB1 0xF9 = 0x00 - 0x07 TEST_BIT 1 = bool(0x00F9 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x009E = C SET_REG1 A = 0x9E temp1.b = A ---------------- REG 0x009E = A SET_REG1 temp1 = 0x9E A = A + E ---------------- REG 0x009E = A REG 0x0007 = E ADD1 0xA5 = 0x9E + 0x07 SET_REG1 A = 0xA5 flag:c = temp1.b u> 0xff - E ---------------- REG 0x009E = temp1 REG 0x0007 = E SUB1 0xF8 = 0xFF - 0x07 CMP_UGT 0 = 0x009E > 0x00F8 SET_FLAG c = 0 C = A ---------------- REG 0x00A5 = A SET_REG1 C = 0xA5 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0007 = DE SUB2 0x0006 = 0x0007 - 0x0001 SET_REG2 DE = 0x0006 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0006 = E SUB1 0xFA = 0x00 - 0x06 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0006 = E TEST_BIT 0 = bool(0x0006 & 0x0080) REG 0x0000 = A REG 0x0006 = E SUB1 0xFA = 0x00 - 0x06 TEST_BIT 1 = bool(0x00FA & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0006 = E SUB1 0xFA = 0x00 - 0x06 TEST_BIT 1 = bool(0x00FA & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00A5 = C SET_REG1 A = 0xA5 temp1.b = A ---------------- REG 0x00A5 = A SET_REG1 temp1 = 0xA5 A = A + E ---------------- REG 0x00A5 = A REG 0x0006 = E ADD1 0xAB = 0xA5 + 0x06 SET_REG1 A = 0xAB flag:c = temp1.b u> 0xff - E ---------------- REG 0x00A5 = temp1 REG 0x0006 = E SUB1 0xF9 = 0xFF - 0x06 CMP_UGT 0 = 0x00A5 > 0x00F9 SET_FLAG c = 0 C = A ---------------- REG 0x00AB = A SET_REG1 C = 0xAB A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0006 = DE SUB2 0x0005 = 0x0006 - 0x0001 SET_REG2 DE = 0x0005 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0005 = E SUB1 0xFB = 0x00 - 0x05 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0005 = E TEST_BIT 0 = bool(0x0005 & 0x0080) REG 0x0000 = A REG 0x0005 = E SUB1 0xFB = 0x00 - 0x05 TEST_BIT 1 = bool(0x00FB & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0005 = E SUB1 0xFB = 0x00 - 0x05 TEST_BIT 1 = bool(0x00FB & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00AB = C SET_REG1 A = 0xAB temp1.b = A ---------------- REG 0x00AB = A SET_REG1 temp1 = 0xAB A = A + E ---------------- REG 0x00AB = A REG 0x0005 = E ADD1 0xB0 = 0xAB + 0x05 SET_REG1 A = 0xB0 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00AB = temp1 REG 0x0005 = E SUB1 0xFA = 0xFF - 0x05 CMP_UGT 0 = 0x00AB > 0x00FA SET_FLAG c = 0 C = A ---------------- REG 0x00B0 = A SET_REG1 C = 0xB0 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0005 = DE SUB2 0x0004 = 0x0005 - 0x0001 SET_REG2 DE = 0x0004 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0004 = E TEST_BIT 0 = bool(0x0004 & 0x0080) REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 TEST_BIT 1 = bool(0x00FC & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0004 = E SUB1 0xFC = 0x00 - 0x04 TEST_BIT 1 = bool(0x00FC & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00B0 = C SET_REG1 A = 0xB0 temp1.b = A ---------------- REG 0x00B0 = A SET_REG1 temp1 = 0xB0 A = A + E ---------------- REG 0x00B0 = A REG 0x0004 = E ADD1 0xB4 = 0xB0 + 0x04 SET_REG1 A = 0xB4 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00B0 = temp1 REG 0x0004 = E SUB1 0xFB = 0xFF - 0x04 CMP_UGT 0 = 0x00B0 > 0x00FB SET_FLAG c = 0 C = A ---------------- REG 0x00B4 = A SET_REG1 C = 0xB4 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0004 = DE SUB2 0x0003 = 0x0004 - 0x0001 SET_REG2 DE = 0x0003 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0003 = E TEST_BIT 0 = bool(0x0003 & 0x0080) REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 TEST_BIT 1 = bool(0x00FD & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0003 = E SUB1 0xFD = 0x00 - 0x03 TEST_BIT 1 = bool(0x00FD & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00B4 = C SET_REG1 A = 0xB4 temp1.b = A ---------------- REG 0x00B4 = A SET_REG1 temp1 = 0xB4 A = A + E ---------------- REG 0x00B4 = A REG 0x0003 = E ADD1 0xB7 = 0xB4 + 0x03 SET_REG1 A = 0xB7 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00B4 = temp1 REG 0x0003 = E SUB1 0xFC = 0xFF - 0x03 CMP_UGT 0 = 0x00B4 > 0x00FC SET_FLAG c = 0 C = A ---------------- REG 0x00B7 = A SET_REG1 C = 0xB7 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0003 = DE SUB2 0x0002 = 0x0003 - 0x0001 SET_REG2 DE = 0x0002 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0002 = E TEST_BIT 0 = bool(0x0002 & 0x0080) REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 TEST_BIT 1 = bool(0x00FE & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0002 = E SUB1 0xFE = 0x00 - 0x02 TEST_BIT 1 = bool(0x00FE & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00B7 = C SET_REG1 A = 0xB7 temp1.b = A ---------------- REG 0x00B7 = A SET_REG1 temp1 = 0xB7 A = A + E ---------------- REG 0x00B7 = A REG 0x0002 = E ADD1 0xB9 = 0xB7 + 0x02 SET_REG1 A = 0xB9 flag:c = temp1.b u> 0xff - E ---------------- REG 0x00B7 = temp1 REG 0x0002 = E SUB1 0xFD = 0xFF - 0x02 CMP_UGT 0 = 0x00B7 > 0x00FD SET_FLAG c = 0 C = A ---------------- REG 0x00B9 = A SET_REG1 C = 0xB9 A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0002 = DE SUB2 0x0001 = 0x0002 - 0x0001 SET_REG2 DE = 0x0001 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0001 = E TEST_BIT 0 = bool(0x0001 & 0x0080) REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0001 = E SUB1 0xFF = 0x00 - 0x01 TEST_BIT 1 = bool(0x00FF & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0001 = 0x0001 & 0x0001 OR 0x0001 = 0x0000 | 0x0001 SET_FLAG c = 1 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 SET_REG1 A = 0xFF flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 CMP_SLT1 1 = -1 < 0 SET_FLAG s = 1 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) XOR 0x0000 = 0x0001 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0000 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 1 = vm_flags[c] SBB1 0xFF = 0x00 - 0x00 - 1 TEST_BIT 1 = bool(0x00FF & 0x0080) AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 1 = vm_flags[s] XOR 0x0000 = 0x0001 ^ 0x0001 goto 23 @ 0x31e ---------------- A = C ---------------- REG 0x00B9 = C SET_REG1 A = 0xB9 temp1.b = A ---------------- REG 0x00B9 = A SET_REG1 temp1 = 0xB9 A = A + E ---------------- REG 0x00B9 = A REG 0x0001 = E ADD1 0xBA = 0xB9 + 0x01 SET_REG1 A = 0xBA flag:c = temp1.b u> 0xff - E ---------------- REG 0x00B9 = temp1 REG 0x0001 = E SUB1 0xFE = 0xFF - 0x01 CMP_UGT 0 = 0x00B9 > 0x00FE SET_FLAG c = 0 C = A ---------------- REG 0x00BA = A SET_REG1 C = 0xBA A = B ---------------- REG 0x0013 = B SET_REG1 A = 0x13 A = adc.b(A, D, flag:c) ---------------- REG 0x0013 = A REG 0x0000 = D FLAG 0 = vm_flags[c] ADC 0x0013 = 0x0013 + 0x0000 + 0 SET_REG1 A = 0x13 B = A ---------------- REG 0x0013 = A SET_REG1 B = 0x13 DE = DE - 1 ---------------- REG 0x0001 = DE SUB2 0x0000 = 0x0001 - 0x0001 SET_REG2 DE = 0x0000 goto 7 @ 0x313 ---------------- A = 0 ---------------- SET_REG1 A = 0x00 A - E ---------------- REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 flag:c = (((test_bit(A, 0x80) ^ 0x1) & test_bit(E, 0x80)) | (test_bit(E, 0x80) & test_bit(A - E, 0x80))) | (test_bit(A - E, 0x80) & (test_bit(A, 0x80) ^ 0x1)) ---------------- REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = E TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = E TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 REG 0x0000 = A REG 0x0000 = E SUB1 0x00 = 0x00 - 0x00 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = A TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG c = 0 temp0.b = A ---------------- REG 0x0000 = A SET_REG1 temp0 = 0x00 A = sbb.b(temp0.b, D, flag:c) ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 SET_REG1 A = 0x00 flag:s = sbb.b(temp0.b, D, flag:c) s< 0 ---------------- REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 CMP_SLT1 0 = 0 < 0 SET_FLAG s = 0 flag:pv = ((test_bit(temp0.b, 0x80) & (test_bit(D, 0x80) ^ 0x1)) & (test_bit(sbb.b(temp0.b, D, flag:c), 0x80) ^ 0x1)) | (((test_bit(temp0.b, 0x80) ^ 0x1) & test_bit(D, 0x80)) & test_bit(sbb.b(temp0.b, D, flag:c), 0x80)) ---------------- REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 AND 0x0000 = 0x0000 & 0x0001 REG 0x0000 = temp0 TEST_BIT 0 = bool(0x0000 & 0x0080) XOR 0x0001 = 0x0000 ^ 0x0001 REG 0x0000 = D TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0001 & 0x0000 REG 0x0000 = temp0 REG 0x0000 = D FLAG 0 = vm_flags[c] SBB1 0x00 = 0x00 - 0x00 - 0 TEST_BIT 0 = bool(0x0000 & 0x0080) AND 0x0000 = 0x0000 & 0x0000 OR 0x0000 = 0x0000 | 0x0000 SET_FLAG pv = 0 if (flag:pv ^ 0x1) then 15 @ 0x31b else 16 ---------------- FLAG 0 = vm_flags[pv] XOR 0x0001 = 0x0000 ^ 0x0001 if (flag:s ^ 0x1) then 17 @ 0x327 else 20 ---------------- FLAG 0 = vm_flags[s] XOR 0x0001 = 0x0000 ^ 0x0001 L = C ---------------- REG 0x00BA = C SET_REG1 L = 0xBA H = B ---------------- REG 0x0013 = B SET_REG1 H = 0x13 jump(pop) ---------------- POP 0x07FC from mem[0x07FC] RET 0xAAAA [32mPASSED[0m triangle_down(100) (5050 is correct) HL = 4 ---------------- SET_REG2 HL = 0x0004 HL = HL + SP {arg3} ---------------- REG 0x0004 = HL REG 0x07FA = SP ADD2 0x07FE = 0x0004 + 0x07FA SET_REG2 HL = 0x07FE C = [HL {arg3}].b ---------------- REG 0x07FE = HL LOAD1 0x4 = mem[0x07FE] SET_REG1 C = 0x04 HL = HL + 1 {arg4} ---------------- REG 0x07FE = HL ADD2 0x07FF = 0x07FE + 0x0001 SET_REG2 HL = 0x07FF B = [HL {arg4}].b ---------------- REG 0x07FF = HL LOAD1 0x0 = mem[0x07FF] SET_REG1 B = 0x00 push(BC) ---------------- REG 0x0004 = BC PUSH mem[0x07F8] = 0x0004 HL = 4 ---------------- SET_REG2 HL = 0x0004 HL = HL + SP {arg1} ---------------- REG 0x0004 = HL REG 0x07F8 = SP ADD2 0x07FC = 0x0004 + 0x07F8 SET_REG2 HL = 0x07FC C = [HL {arg1}].b ---------------- REG 0x07FC = HL LOAD1 0x7 = mem[0x07FC] SET_REG1 C = 0x07 HL = HL + 1 {arg2} ---------------- REG 0x07FC = HL ADD2 0x07FD = 0x07FC + 0x0001 SET_REG2 HL = 0x07FD B = [HL {arg2}].b ---------------- REG 0x07FD = HL LOAD1 0x0 = mem[0x07FD] SET_REG1 B = 0x00 push(BC) ---------------- REG 0x0007 = BC PUSH mem[0x07F6] = 0x0007 call(0x5df) ---------------- CALL 0x05DF AF = pop ---------------- POP 0x07F4 from mem[0x07F4] SET_REG2 AF = 0xBACC BC = pop ---------------- POP 0x07F6 from mem[0x07F6] SET_REG2 BC = 0x0007 DE = pop ---------------- POP 0x07F8 from mem[0x07F8] SET_REG2 DE = 0x0004 push(DE) ---------------- REG 0x0004 = DE PUSH mem[0x07F8] = 0x0004 push(BC) ---------------- REG 0x0007 = BC PUSH mem[0x07F6] = 0x0007 push(AF) ---------------- REG 0xBACC = AF PUSH mem[0x07F4] = 0xBACC tailcall(0x5e5) ---------------- TAILCALL 0x05E5 AF = pop ---------------- POP 0x07F2 from mem[0x07F2] SET_REG2 AF = 0xBAC2 AF = pop ---------------- POP 0x07F4 from mem[0x07F4] SET_REG2 AF = 0xBACC jump(pop) ---------------- POP 0x07F6 from mem[0x07F6] RET 0x0007 [31mFAILED[0m multiply(4,7) (2045 is incorrect, expected 28)