DUP (predicate)

Broadcast indexed predicate element

Broadcast indexed element of the source predicate in the corresponding elements of the destination predicate. The indexed predicate element is selected by the sum of index base register and optional index offset modulo the total number of predicate elements. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.

313029282726252423222120191817161514131211109876543210
00100101i1tszh1tszlRm01Pg0Pn0Pd
S

DUP <Pd>.<T>, <Pg>/Z, <Pn>.<T>[<Wm>{, #<imm>}]

if !HaveSME() then UNDEFINED; bits(5) imm = i1:tszh:tszl; case tszh:tszl of when '0000' UNDEFINED; when '1000' esize = 64; offset = UInt(imm<4>); when 'x100' esize = 32; offset = UInt(imm<4:3>); when 'xx10' esize = 16; offset = UInt(imm<4:2>); when 'xxx1' esize = 8; offset = UInt(imm<4:1>); integer g = UInt(Pg); integer n = UInt(Pn); integer d = UInt(Pd); integer m = UInt('011':Rm);

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T>

Is the size specifier, encoded in tszh:tszl:

tszh tszl <T>
0 000 RESERVED
x xx1 B
x x10 H
x 100 S
1 000 D
<Pg>

Is the name of the governing scalable predicate register, encoded in the "Pg" field.

<Pn>

Is the name of the source scalable predicate register, encoded in the "Pn" field.

<Wm>

Is the 32-bit name of the index base register W12-W15, encoded in the "Rm" field.

<imm>

Is the optional element index, defaulting to 0, in the range 0 to one less than the number of vector elements in a 128-bit vector register, encoded in "i1:tszh:tszl".

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(PL) operand = P[n]; bits(32) base = X[m]; integer index = (UInt(base) + offset) MOD elements; bits(PL) result; bit value = ElemP[operand, index, esize]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then ElemP[result, e, esize] = value; else ElemP[result, e, esize] = '0'; P[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.21, AdvSIMD v29.05, pseudocode v2021-06_xml, sve v2021-06_rc2b ; Build timestamp: 2021-06-28T16:38

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